Abstract: A random access memory (RAM) having a prescribed number of bits defining a word length includes memory cells that enable selective overwriting on a bit-by-bit basis. Each memory cell includes a logic gate for generating a gating signal in response to a supplied write signal and a bit enable signal. The gating signal selectively connects the bistable latch of the memory cell to a voltage source to enable storage of the supplied data bit. Hence, selected bits can be written to an address word, without overwriting the unselected bits in the stored word, by supplying a mask signal that selectively drives the logic gates of the selected bits. The mask signal can also be used to configure a RAM as a dynamic-width memory, enabling use of the RAM for variable-width storage applications without the necessity of external decoding logic.

Abstract: A random access memory (RAM) having a prescribed number of bits defining a word length includes memory cells that enable selective overwriting on a bit-by-bit basis. Each memory cell includes a logic gate for generating a gating signal in response to a supplied write signal and a bit enable signal. The gating signal selectively connects the bistable latch of the memory cell to a voltage source to enable storage of the supplied data bit. Hence, selected bits can be written to an address word, without overwriting the unselected bits in the stored word, by supplying a mask signal that selectively drives the logic gates of the selected bits. The mask signal can also be used to configure a RAM as a dynamic-width memory, enabling use of the RAM for variable-width storage applications without the necessity of external decoding logic.