Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.

Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

Abstract: A method includes forming a first amorphous material, forming a second amorphous material over and in contact with the first material, removing a portion of the second material and the first material to form pillars, and exposing the materials to a temperature between a crystallization temperature of the first material and a crystallization temperature of the second material. The first material and the second material each comprise at least one element selected from the group consisting of silicon and germanium. The second material exhibits a crystallization temperature different than a crystallization temperature of the first material. Semiconductor structures, memory devices, and systems are also disclosed.

Abstract: A transistor comprises a pair of source/drain regions having a channel region there-between. A gate is adjacent the channel region with a gate insulator being between the gate and the channel region. A fixed-charge material is adjacent the source/drain regions. Insulating material is between the fixed-charge material and the source/drain regions. The insulating material and the fixed-charge material comprise different compositions relative one another. The fixed-charge material has charge density of at least 1 x 1011 charges/cm2.

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.

Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

Abstract: Some embodiments include a capacitor having a container-shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.

Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

Abstract: A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another.

Abstract: A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another.

Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

Abstract: Some embodiments include a capacitor having a container-shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.

Abstract: An anti-reflection coating has an average total reflectance of less than 10%, for example less than 5.9% such as from 4.9% to 5.9%, over a spectrum of wavelengths of 400-1100 nm and a range of angles of incidence of 0-90 degrees with respect to a surface normal of the anti-reflection coating. An anti-reflection coating has a total reflectance of less than 10%, for example less than 6% such as less than 4%, over an entire spectrum of wavelengths of 400-1600 nm and an entire range of angles of incidence of 0-70 degrees with respect to a surface normal of the anti-reflection coating.