Patents by Inventor Sameer D. Parab
Sameer D. Parab has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8946912Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: GrantFiled: December 31, 2013Date of Patent: February 3, 2015Assignee: Intersil Americas LLCInventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
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Publication number: 20140113444Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: ApplicationFiled: December 31, 2013Publication date: April 24, 2014Applicant: INTERSIL AMERICAS INC.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert Lomenick, Chris A. McCarty
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Patent number: 8652960Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: GrantFiled: December 18, 2012Date of Patent: February 18, 2014Assignee: Intersil Americas Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
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Patent number: 8569896Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: GrantFiled: June 26, 2012Date of Patent: October 29, 2013Assignee: Intersil Americas Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
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Publication number: 20120261836Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Applicant: INTERSIL AMERICAS INC.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty
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Patent number: 8274160Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.Type: GrantFiled: June 28, 2010Date of Patent: September 25, 2012Assignee: Intersil Americas Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
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Publication number: 20100261344Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.Type: ApplicationFiled: June 28, 2010Publication date: October 14, 2010Applicant: INTERSIL AMERICAS INC.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty
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Patent number: 7795130Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.Type: GrantFiled: April 19, 2007Date of Patent: September 14, 2010Assignee: Intersil Americas Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
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Patent number: 7224074Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.Type: GrantFiled: December 19, 2005Date of Patent: May 29, 2007Assignee: Intersil Americas Inc.Inventors: John T Gasner, Michael D Church, Sameer D Parab, Paul E Bakeman, Jr., David A Decrosta, Robert Lomenic, Chris A McCarty
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Patent number: 7005369Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.Type: GrantFiled: October 31, 2003Date of Patent: February 28, 2006Assignee: Intersil American Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty