Patents by Inventor Sameer D. Parab

Sameer D. Parab has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8946912
    Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: February 3, 2015
    Assignee: Intersil Americas LLC
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
  • Publication number: 20140113444
    Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
    Type: Application
    Filed: December 31, 2013
    Publication date: April 24, 2014
    Applicant: INTERSIL AMERICAS INC.
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert Lomenick, Chris A. McCarty
  • Patent number: 8652960
    Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 18, 2014
    Assignee: Intersil Americas Inc.
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
  • Patent number: 8569896
    Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: October 29, 2013
    Assignee: Intersil Americas Inc.
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
  • Publication number: 20120261836
    Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
    Type: Application
    Filed: June 26, 2012
    Publication date: October 18, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty
  • Patent number: 8274160
    Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: September 25, 2012
    Assignee: Intersil Americas Inc.
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
  • Publication number: 20100261344
    Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.
    Type: Application
    Filed: June 28, 2010
    Publication date: October 14, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty
  • Patent number: 7795130
    Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: September 14, 2010
    Assignee: Intersil Americas Inc.
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
  • Patent number: 7224074
    Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: May 29, 2007
    Assignee: Intersil Americas Inc.
    Inventors: John T Gasner, Michael D Church, Sameer D Parab, Paul E Bakeman, Jr., David A Decrosta, Robert Lomenic, Chris A McCarty
  • Patent number: 7005369
    Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: February 28, 2006
    Assignee: Intersil American Inc.
    Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty