Patents by Inventor Sameer Hemchand Jain

Sameer Hemchand Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Two-step silicide formation
    Patent number: 8652914
    Abstract: An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Sameer Hemchand Jain, Reinaldo Ariel Vega
  • TWO-STEP SILICIDE FORMATION
    Publication number: 20120223372
    Abstract: An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emre Alptekin, Sameer Hemchand Jain, Reinaldo Ariel Vega
  • Planar silicide semiconductor structure
    Patent number: 8236637
    Abstract: A planar silicide structure and method of fabrication is disclosed. A FET having a silicided raised source-drain structure is formed where the height of the source-drain structures are the same as the height of the gates, simplifying the process of forming contacts on the FET. One embodiment utilizes a replacement metal gate FET and another embodiment utilizes a gate-first FET.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Henry K. Utomo, Sameer Hemchand Jain, Ravikumar Ramachandran, Cung D. Tran
  • Planar Silicide Semiconductor Structure
    Publication number: 20120074503
    Abstract: A planar silicide structure and method of fabrication is disclosed. A FET having a silicided raised source-drain structure is formed where the height of the source-drain structures are the same as the height of the gates, simplifying the process of forming contacts on the FET.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: International Business Machines Corporation
    Inventors: Henry K. Utomo, Sameer Hemchand Jain, Ravikumar Ramachandran, Cung D. Tran