Patents by Inventor Sameer Kapoor

Sameer Kapoor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12210898
    Abstract: The present application discloses a method, system, and computer system for dynamically managing or distributing models across a plurality of shards. The method includes determining that a first model is to be added to a first shard of a plurality of shards, the first shard being determined based at least in part on a predetermined cost function, adding the first model to the first shard, and restarting the first shard. The first model is associated with a first tenant. The first shard comprises at least one second model that is associated with a second tenant.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: January 28, 2025
    Assignee: Workday, Inc.
    Inventors: Sameer Kapoor, Sergei Winitzki
  • Patent number: 10515168
    Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: December 24, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Pankaj P. Chauhan, Sameer Kapoor, Saurabh Jain, Kunal Bindal, Bryan D. Bowyer, Andres R. Takach, Peter P. Gutberlet, Gagandeep Singh, Maheshinder Goyal
  • Patent number: 9817929
    Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: November 14, 2017
    Assignee: Calypto Design Systems, Inc.
    Inventors: Pankaj P. Chauhan, Sameer Kapoor, Saurabh Jain, Kunal Bindal, Bryan D. Bowyer, Andres R. Takach, Peter P. Gutberlet, Gagandeep Singh, Maheshinder Goyal