Patents by Inventor Sameer KP

Sameer KP has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10380039
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Niranjan L. Cooray, Satyeshwar Singh, Sameer KP, Ankur N. Shah, Kun Tian, Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Pattabhiraman K, David Puffer, David J. Cowperthwaite, Rajesh M. Sankaran
  • Publication number: 20190147640
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: October 29, 2018
    Publication date: May 16, 2019
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Patent number: 10275924
    Abstract: Techniques for managing a three-dimensional (3D) graphics display mode are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics processing module, and the graphics processing module may be operative by the processor circuit to execute a graphics context in a 3D display mode if a 3D-aware graphics context data structure includes an entry corresponding to the graphics context or to execute the graphics context in a non-3D display mode if the 3D-aware graphics context data structure does not include an entry corresponding to the graphics context. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: April 30, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sameer Kp, Sanjeev Tiwari
  • Publication number: 20190087983
    Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 21, 2019
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Hugues Labbe, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh
  • Publication number: 20190041955
    Abstract: Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 7, 2019
    Applicant: INTEL CORPORATION
    Inventors: Seh Kwa, Nausheen Ansari, Sameer Kp
  • Publication number: 20190043442
    Abstract: A processing unit, device, system and method are described. A processing unit can be configured to access frame data and associated metadata. The processing unit can be configured to send the associated metadata from a processing unit to a display controller on a channel that is different than a channel configured to send the frame data.
    Type: Application
    Filed: July 12, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Sameer KP, Vinay Angadi, Yiting Lee, Roland Wooster, Sagar Karalatti
  • Patent number: 10152822
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Patent number: 10134360
    Abstract: By converting a first color space to a second color space, using a two-dimensional lookup table in said second color space, and converting from said second color space to said first color space, it may be possible to use one or more two-dimensional lookup tables (LUTs) to do a task conventionally handled by three-dimensional lookup tables. This may reduce storage requirements and memory bandwidth requirements in some embodiments. In general a color pixel with N color components can be processed with n number of M dimensional LUT where M<N and n is some chosen positive integer number.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Susanta Bhattacharjee, Sameer Kp
  • Publication number: 20180308277
    Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp, Jonathan Kennedy, Abhishek R. Appu, Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Slawomir Grajewski, Gabor Liktor, David M. Cimini, Andrew T. Lauritzen, Travis T. Schluessler, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Kai Xiao, Ankur N. Shah, Altug Koker
  • Publication number: 20180307305
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Ravindra A. Babu, Sashank Sms Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Patent number: 10109078
    Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Hugues Labbe, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh
  • Publication number: 20180293760
    Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Hugues Labbe, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh
  • Publication number: 20180293183
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: NIRANJAN L. COORAY, ABHISHEK R. APPU, ALTUG KOKER, JOYDEEP RAY, BALAJI VEMBU, PATTABHIRAMAN K, DAVID PUFFER, DAVID J. COWPERTHWAITE, RAJESH M. SANKARAN, SATYESHWAR SINGH, SAMEER KP, ANKUR N. SHAH, KUN TIAN
  • Publication number: 20180293961
    Abstract: Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Hugues Labbe, Karthik Vaidyanathan, Prasoonkumar Surti, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy
  • Publication number: 20180286345
    Abstract: Methods for controlling refresh rate during panel self-refresh 2 (PSR2), are described. Those methods and associated devices may include sending, via a source interface controller enabled for PSR2, a display port configuration data (DPCD) value of high, a data transfer request packet to include a low refresh rate target value of a display device; receiving, via the sink interface controller, the DPCD high value; and entering, via the sink interface controller, a low refresh rate at target values when the source interface controller enters static or sleep mode, and wherein the refresh rate is dynamically controlled during PSR2.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Yiting Lee, Mathangi Srinivasan, Suketu J. Shah, Sameer KP, Curly Tsao
  • Publication number: 20180286105
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Publication number: 20170206864
    Abstract: Methods, apparatus, and articles of manufacture to provide extended graphics processing capabilities are disclosed. A disclosed example method involves sending a display panel parameter to a shared library module. The display panel parameter is sent by a programmable driver interface in communication between the shared library module and a graphics hardware device driver. The shared library module includes a first graphics processing capability. The graphics hardware device driver includes a second graphics processing capability different from the first graphics processing capability. The example method also involves performing a render operation via the programmable driver interface on a frame buffer based on the first graphics processing capability. The first graphics processing capability is received at the programmable driver interface from the shared library module based on the display panel parameter. The frame buffer is output to a display.
    Type: Application
    Filed: April 1, 2017
    Publication date: July 20, 2017
    Inventors: Sameer Kp, Selvakumar Panneer, Susanta Bhattacharjee, Mrinalini Attaluri
  • Publication number: 20170140498
    Abstract: Methods, apparatus, and articles of manufacture to provide extended graphics processing capabilities are disclosed. A disclosed example method involves sending a display panel parameter to a shared library module. The display panel parameter is sent by a programmable driver interface in communication between the shared library module and a graphics hardware device driver. The shared library module includes a first graphics processing capability. The graphics hardware device driver includes a second graphics processing capability different from the first graphics processing capability. The example method also involves performing a render operation via the programmable driver interface on a frame buffer based on the first graphics processing capability. The first graphics processing capability is received at the programmable driver interface from the shared library module based on the display panel parameter. The frame buffer is output to a display.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 18, 2017
    Inventors: Sameer Kp, Selvakumar Panneer, Susanta Bhattacharjee, Mrinalini Attaluri
  • Patent number: 9600055
    Abstract: Particular embodiments described herein provide an apparatus to control power consumption including logic, at least partially including hardware logic, to determine whether an electronic device is using an external display, determine whether a user input has been received by the electronic device within a predetermined time period when the electronic device is using the external display, and control power consumption by a display of the electronic device based at least in part on whether user input has been received within the predetermined time period.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventor: Sameer KP
  • Patent number: 9530386
    Abstract: Methods, apparatus, and articles of manufacture to provide extended graphics processing capabilities are disclosed. A disclosed example method involves sending a display panel parameter to a shared library module. The display panel parameter is sent by a programmable driver interface in communication between the shared library module and a graphics hardware device driver. The shared library module includes a first graphics processing capability. The graphics hardware device driver includes a second graphics processing capability different from the first graphics processing capability. The example method also involves performing a render operation via the programmable driver interface on a frame buffer based on the first graphics processing capability. The first graphics processing capability is received at the programmable driver interface from the shared library module based on the display panel parameter. The frame buffer is output to a display.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Sameer Kp, Selvakumar Panneer, Susanta Bhattacharjee, Mrinalini Attaluri