Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

Abstract: The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.

Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

Abstract: The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.

Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

Abstract: A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.

Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138).