Patents by Inventor Sameer R. PAITAL

Sameer R. PAITAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240222293
    Abstract: Technologies for ribbon field-effect transistors with variable fin numbers are disclosed. In an illustrative embodiment, a stack of semiconductor fins is formed, with each semiconductor fin having a source region, a channel region, and a drain region. Some or all of the channel regions can be selectively removed, allowing for the drive and/or leakage current to be tuned. In some embodiments, one or more of the semiconductor fins near the top of the stack can be removed. In other embodiments, one or more of the semiconductor fins at or closer to the bottom of the stack can be removed.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Kristof Darmawikarta, Srinivas V. Pietambaram, Gang Duan, Siddharth Alur Narasimha Krishna, Sameer R. Paital, Helme A. Castro De la Torre
  • Publication number: 20230395467
    Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Applicant: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Kristof Darmawikarta, Tarek A. Ibrahim, Jeremy D. Ecton, Brandon Christian Marin, Gang Duan, Suddhasattwa Nad, Yi Yang, Benjamin T. Duong, Junxin Wang, Sameer R. Paital
  • Publication number: 20230395445
    Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Applicant: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Kristof Darmawikarta, Tarek A. Ibrahim, Jeremy D. Ecton, Brandon Christian Marin, Gang Duan, Suddhasattwa Nad, Yi Yang, Benjamin T. Duong, Junxin Wang, Sameer R. Paital
  • Publication number: 20190206786
    Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first surface, one or more second conductive contacts on a second surface opposite the first surface, a dielectric layer between the first and the second surfaces, and an embedded capacitor on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded capacitor comprises a first metal layer on the dielectric layer, a thin film dielectric material on a surface of the metal layer, a second metal layer on the surface of the first metal layer, and a third metal layer on the thin film dielectric material. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Aleksandar ALEKSOV, Kristof DARMAWIKARTA, Sandeep GAAN, Srinivas V. PIETAMBARAM, Sameer R. PAITAL