Abstract: An over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells during programming operations so as to render high endurance. Sensing circuitry (23) is used to detect column leakage current indicative of an over-erased bit. If an over-erased bit is determined, a pulse counter (25) is activated so as to apply programming pulses to the control gate of the selected memory cell so as to program back the negative threshold voltage of the over-erased bit to a positive voltage.

Abstract: A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V.sub.CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.

Abstract: A method of improving the integrity of silicon dioxide is disclosed. As applicable, for example, to the formation of oxide regions in an integrated circuit (such as thin, gate oxides) an implantation of nitrogen ions is performed prior to high temperature processing steps of the circuit fabrication. High temperature steps then result in silicon-nitrogen compounds being formed at the interfaces of the silicon dioxide regions with subjacent and superjacent regions of the integrated circuit structure. These compounds prevent the incursion of impurities into the silicon dioxide which would degrade its quality.