Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. The various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure.

Abstract: Techniques are provided herein to form semiconductor devices having different gate lengths on the same die. In an example, any number of first semiconductor devices includes first gate structures around first semiconductor regions and any number of second semiconductor devices include second gate structures around second semiconductor regions. The first gate structures have a first gate length around the first semiconductor regions and the second gate structures have a second gate length around the second semiconductor regions with the second gate length being greater than the first gate length. An upper thickness of each the first and second gate structures may be the same, despite the gate length diversity. The first semiconductor devices include first inner spacer structures around ends of the first semiconductor regions that have a greater lateral thickness compared to second inner spacer structures around ends of the second semiconductor regions of the second semiconductor devices.

Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer.