Abstract: A bandgap apparatus includes an error amplifier; a bandgap core including 2 BJT devices and core resistors for proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) current generations; a reference resistor for reference voltage generation; an NMOS current mirror having NMOS devices; a PMOS current mirror having PMOS devices; and 4 switches for controlling operation in a high-power mode or a low-power mode, wherein the high-power mode consumes more power than the low-power mode, wherein the error amplifier is switched on and the NMOS current mirror is switched off in the high-power mode, or the error amplifier is switched off and the NMOS current mirror is switched on in the low-power mode.

Abstract: An apparatus includes a poly current generator circuit, which includes a fractional bandgap circuit, or a bandgap voltage reference circuit and a current reference generator, an adaptive bias current generator, a frequency generator to generate an output clock signal having a select frequency, wherein the frequency generator includes a current starved ring oscillator that comprises n identical cascaded stages connected in a shape of a ring, wherein an output of the nth cascaded stage is fed back as an input of the first cascaded stage, wherein n is an odd number greater than or equal to 3; and clock buffers configured to buffer the output clock signal generated by the frequency generator for distribution.

Abstract: A load detection circuit includes a variable current source circuit having a first input connected to a power supply, a second input, and a first output connected to an output load; a switched capacitor circuit having a third input connected to an external voltage reference signal, a fourth input connected to the first output of the variable current source, a fifth input connected to ground, a sixth input, and a second output; a comparator having a seventh input connected to the second output of the switched capacitor circuit, an eighth input connected to the first output of the variable current source, and a third output; an edge detector having a ninth input connected to the third output of the comparator, and a fourth output; and a digital controller having a fifth output connected to the variable current source and a sixth output connected to the switched capacitor circuit.

Abstract: A band-gap reference circuit includes a band-gap voltage reference core to provide a reference voltage; a low impedance block; three capacitors; two transmission gates to connect and disconnect the capacitors; and two digital control blocks. The three capacitors includes an output capacitor connected at an output of the low impedance block to ground; a small capacitor connected to an output of the band-gap voltage reference core; and a large capacitor connected to the two transmission gates. The band-gap voltage reference core includes an operational amplifier, wherein an output of the operational amplifier connects to an input of the low impedance block and the small capacitor, wherein the small capacitor is also connected to ground; and a combination of bipolar junction transistors, MOS-FET, resistors, capacitors, or FinFET devices that provides a reference voltage.

Abstract: A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a voltage clamp circuit which limits the supply level for a first inverter. The clamp circuit having a first input connected to a supply, a second input connected to chip enable, and a first output.

Abstract: An automatically reconfigurable Buck-Boost DC-DC converter having an input supply and an output voltage includes a linear regulator (LDO) for Buck configuration; a switched-capacitor DC-DC converter; a capacitor and switch array, and a gain selector to switch between the linear regulator (LDO) when an output DC level is higher than an input DC level (Buck configuration) and the switched-capacitor DC-DC converter when the output DC level is lower than the input DC level (Boost configuration).

Abstract: A load detection circuit includes a variable current source circuit having a first input connected to a power supply, a second input, and a first output connected to an output load; a switched capacitor circuit having a third input connected to an external voltage reference signal, a fourth input connected to the first output of the variable current source, a fifth input connected to ground, a sixth input, and a second output; a comparator having a seventh input connected to the second output of the switched capacitor circuit, an eighth input connected to the first output of the variable current source, and a third output; an edge detector having a ninth input connected to the third output of the comparator, and a fourth output; and a digital controller having a fifth output connected to the variable current source and a sixth output connected to the switched capacitor circuit.

Abstract: A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a voltage clamp circuit which limits the supply level for a first inverter. The clamp circuit having a first input connected to a supply, a second input connected to chip enable, and a first output.