Abstract: A substrate lift pin assembly, a system including the assembly, and methods of using the same are disclosed. The assembly can include one or more lift pins and a sensor to determine one or more of presence and condition information of the one or more lift pins. The system can be configured to provide an alarm and/or to cease operations based on the presence and/or condition information.

Abstract: A wafer boat configured to support one or more wafers is provided. The wafer boat includes a first pillar, second pillar and third pillar, each having a plurality of protrusion elements. Top surfaces of the first, second and third pillar are coupled to a triangular top member and bottom surfaces of the first, second and third pillar are coupled to a triangular bottom member. The wafer boat defines a central axis that extends vertically and is parallel to the first, second and third pillar. The protrusion elements extend towards the central axis to define a plurality of wafer slots, wherein each wafer slot is configured to support a wafer.

Abstract: Transfer chambers, semiconductor processing systems including transfer chambers, and methods for preventing moisture from entering a transfer chamber are provided. The transfer chambers disclosed include one or more gas distributors for forming a gas curtain across openings in the transfer chamber thereby preventing moisture from entering the transfer chamber.

Abstract: An apparatus with a wafer temperature control capabilities is presented. The apparatus comprising: a plate configured to control a temperature of the wafer placed on it, a cool tank and a hot tank to store a cool and hot fluid respectively, a cooling & heating device to cool & heat the fluid in the cool tank and the hot tank respectively, an exit switch valve configured to control a direction of the fluid coming out of the plate, an input switch valve configured to control a direction of the fluid going into the plate, a first fluid line, a second fluid line, a third fluid line, and a fourth fluid line; a pump configured to pump the fluid in the input path into the plate; and a controller configured to control an opening state of the exit switch valve and the input switch valve.

Abstract: A load lock arrangement includes a load lock body that has an upper plate defining an upper accessory seat at the upper accessory seat aperture, an intermediate plate spaced apart from the upper plate defining an intermediate accessory seat at the intermediate accessory seat aperture, and a lower plate separated from the upper plate by the intermediate plate defining a lower accessory seat at the lower accessory seat aperture. A first accessory plate is fixed to the upper accessory seat and a second accessory plate is fixed to the lower accessory seat. The upper accessory seat aperture, the intermediate accessory seat aperture and the lower accessory seat aperture are vertically aligned to form a load lock body aperture. Semiconductor processing systems and methods of making load lock arrangements are also described.

Abstract: A substrate preheating module is presented. According to an embodiment of the present disclosure, the module comprising a chamber configured to receive more than one substrates from an equipment front end module (EFEM), a first opening disposed on a wall of the chamber adjacent to the EFEM, a gas inlet configured to deliver a gas from an outer gas source into the chamber, a first valve disposed at the gas inlet and configured to control the input of the gas into the chamber, an exhaust vent configured to pump out the gas from the chamber, a second valve disposed at the exhaust vent and configured to control the exhaust of the gas from the chamber and a heater configured to heat the gas in the chamber. The module may further comprise a controller to control the valves and heater.

Abstract: An apparatus for cooling substrates is presented. The apparatus comprising: a chamber housing; a first port disposed in the first wall configured to be sealable from a first environment; a second port disposed in the second wall configured to be sealable from a second environment; a first support disposed between the top and the bottom of the chamber housing; a second support disposed between the first support and the bottom of the chamber housing; a first body disposed just below the top wall; and a second body disposed just above the bottom wall, wherein an emissivity of the first body and an emissivity of the second body are equal to or greater than a predetermined threshold.

Abstract: Systems and methods for controlling device performance variability during manufacturing of a device on wafers are disclosed. The system includes a process platform, on-board metrology (OBM) tools, and a first server that stores a machine-learning based process control model. The first server combines virtual metrology (VM) data and OBM data to predict a spatial distribution of one or more dimensions of interest on a wafer. The system further comprises an in-line metrology tool, such as SEM, to measure the one or more dimensions of interest on a subset of wafers sampled from each lot. A second server having a machine-learning engine receives from the first server the predicted spatial distribution of the one or more dimensions of interest based on VM and OBM, and also receives SEM metrology data, and updates the process control model periodically (e.g., wafer-to-wafer, lot-to-lot, chamber-to-chamber etc.) using machine learning techniques.

Abstract: Load lock arrangements, semiconductor processing systems including such load lock arrangements, and associated methods for performing parallel processes within such load lock arrangement are disclosed. The load lock arrangements disclosed include an alignment assembly disposed within a load lock body and configured for aligning a substrate within the interior of the load lock body while in parallel reducing the pressure within the load lock body.

Abstract: Substrate processing systems and methods include sealing a gate valve connecting a first chamber (e.g., a load-lock module) and a second chamber (e.g., an equipment front end module), wherein a first side of the first chamber connects to layer deposition equipment and a second side of the first chamber connects to the second chamber via the gate valve. The second chamber receives (i) incoming substrates to be supplied to the first chamber and (ii) outgoing substrates to be removed from the first chamber. In use, a processed substrate is moved from the layer deposition equipment into the first chamber. This processed substrate is cooled by transferring inert gas from the second chamber into the first chamber and into contact with the processed substrate, thereby transferring heat from the processed substrate to the inert gas. After passing over the processed substrate, the inert gas is exhausted from the first chamber.

Abstract: Substrate processing systems have expanded substrate processing capabilities. In some examples, this may be accomplished by providing an inboard substrate handling chamber (e.g., with six facets or side walls) and an outboard substrate handling chamber (e.g., with five facets or side walls). The inboard substrate handling chamber may be connected with additional substrate processing chambers. The inboard substrate handling chamber may be connected to the outboard substrate handling chamber by an additional outboard load-lock module. These features enable a manufacturer to increase the number of substrate processing chambers in a substrate processing system or line.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.

Abstract: Thermal breaks and/or gaps between portions of interfacing surfaces of two chambers reduce heat transfer between the chambers. An interface surface (e.g., of a gate valve) includes (i) a base surface; (ii) a raised ring surface extending outward beyond the base surface, wherein the raised ring surface extends around a gate valve access opening; (iii) a seal support surface extending around the raised ring surface; and (iv) at least one raised boss surface extending outward beyond the base surface. The interface surface defines an outer perimeter having a total interface area. The raised ring surface and raised boss surface(s) define at least a portion of a total contacting surface area of the interface surface that is spaced outward from the base surface. The total contacting surface area of the interface surface is less than 10% of the total interface area and/or less than 10% of the base surface's surface area.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, printed circuit board (PCB) assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a substrate core (e.g., a core structure) is implanted with dopants to achieve a desired bulk resistivity or conductivity. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: Embodiments of apparatus and methods for counting cells in a liquid sample are provided herein. In some embodiments, an apparatus for counting cells in a liquid sample includes: a flow-splitting chamber fluidly coupled to a collection chamber; an input tube configured to deliver a liquid sample to the flow-splitting chamber; a spaced apart array of posts along a flow path configured to redirect the liquid sample into a plurality of streams; a plurality of sensing zones corresponding to the plurality of streams; and a plurality of sensing electrodes, wherein each sensing electrode is disposed in a corresponding sensing zone of the plurality of sensing zones and configured to detect a change in electrical impedance as the liquid sample flows through the plurality of sensing zones.

Abstract: A load lock arrangement includes a load lock body having an upper plate member defining an upper accessory seat, an intermediate plate member spaced apart from the upper plate member and defining an intermediate accessory seat, and a lower plate member separated from the upper plate member by the intermediate plate member and defining a lower accessory seat. One of an upper heater and an upper accessory seat blanking plate is fixed to the upper accessory seat; one of an upper chill plate and an intermediate accessory seat blanking plate fixed to the intermediate accessory seat; and one of a lower chill plate, a lower heater, and a lower accessory seat blanking plate fixed to the lower accessory seat. Semiconductor processing systems, methods of making load lock arrangements, and material layer deposition methods are also described.

Abstract: The present disclosure relates to thin-form-factor semiconductor device packages, and methods and systems for forming the same. Embodiments of the disclosure include methods and apparatus for forming semiconductor device packages that include frames that are coated with a layer of a coupling agent on which subsequently layers are formed. The utilization of the coupling agent between the frame and subsequently formed layers enhances the thermo-mechanical reliability of the package frames by mitigating the stress induced by any subsequently formed insulation layers and/or RDLs, and by providing improved coupling between such layers and the relatively smooth surfaces of the frames.

Abstract: Methods and apparatus of bioreactors for therapeutic cells manufacturing are provided herein. In some embodiments, a bioreactor includes: an upper bioreactor reservoir configured to perform multiple cell therapy manufacturing process steps including genetic modification and expansion to a plurality of cells disposed therein, wherein the upper bioreactor reservoir includes a plurality of ports for delivering fluids into and out of the upper bioreactor reservoir; a lower bioreactor compartment configured to hold a suspension comprising a molecular species; and a membrane disposed between the lower bioreactor compartment and the upper bioreactor reservoir, wherein the membrane includes a plurality of micro-straws extending through the membrane and into the upper bioreactor reservoir to transfect the plurality of cells with the molecular species.

Abstract: A gas distribution hub for a plasma chamber. The hub has a nozzle including a plurality of inner gas injection passage and a plurality of outer gas injection passages. The first plurality of gas injection passages are angularly spaced-apart arcuate channels at a first radial distance from a center of the hub, and the second plurality of gas injection passages are angularly spaced apart arcuate channels at a different second radial distance from the center of the hub.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, printed circuit board (PCB) assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a substrate core (e.g., a core structure) is implanted with dopants to achieve a desired bulk resistivity or conductivity. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.