Abstract: A memory controller and a method for controlling a memory including at least one memory bank including a plurality of storage locations. The memory controller receives memory access requests over a bus in a digital computer system and, in response initiates a memory access operation in connection with a storage location. The memory controller comprises a memory access control circuit that receives memory access requests over the bus and for performing a memory access operation in connection with a storage location in response thereto. A memory refresh control circuit includes a yellow refresh control circuit and a red refresh control circuit, both of which control refresh of the memory bank(s). The yellow refresh control circuit initiates a refresh operation in connection with a memory bank while the memory access control circuit is performing a memory access operation.