Patents by Inventor Sami Issa
Sami Issa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8159861Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: GrantFiled: April 20, 2010Date of Patent: April 17, 2012Assignee: Broadcom CorporationInventor: Sami Issa
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Publication number: 20100202190Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node.Type: ApplicationFiled: April 20, 2010Publication date: August 12, 2010Inventor: Sami Issa
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Patent number: 7706170Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: GrantFiled: November 25, 2008Date of Patent: April 27, 2010Inventor: Sami Issa
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Patent number: 7519925Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability.Type: GrantFiled: May 27, 2005Date of Patent: April 14, 2009Assignee: Texas Instruments IncorporatedInventors: Sami Issa, Uming Ko, David Scott
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Publication number: 20090080235Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: ApplicationFiled: November 25, 2008Publication date: March 26, 2009Inventor: Sami Issa
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Patent number: 7457148Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: GrantFiled: September 25, 2007Date of Patent: November 25, 2008Assignee: Broadcom CorporationInventor: Sami Issa
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Publication number: 20080013367Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: ApplicationFiled: September 25, 2007Publication date: January 17, 2008Inventor: Sami Issa
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Patent number: 7274588Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: GrantFiled: March 29, 2005Date of Patent: September 25, 2007Assignee: Broadcom CorporationInventor: Sami Issa
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Patent number: 7197733Abstract: A single integrated circuit (12). The integrated circuit comprises a first circuit (14x) having a data path, the first circuit consisting of a first number of logic gates for performing a plurality of logic functions. The integrated circuit also comprises a circuit (22x) for indicating a potential speed capability of the data path. The circuit for indicating comprises a second number of logic gates (82, 92) for performing the plurality of logic functions, wherein the second number is less than the first number. The circuit for indicating also comprises additional circuitry (88, 98) for representing parasitic characteristics in the data path.Type: GrantFiled: July 11, 2006Date of Patent: March 27, 2007Assignee: Texas Instruments IncorporatedInventors: Sami Issa, Baher Haroun, Shakti S Rath
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Patent number: 7162652Abstract: A power management system (12) in an electronic device (10). The system comprises circuitry (14x), responsive to at least one system parameter, for providing data processing functionality, where the circuitry for providing data processing functionality comprises a data path (CPx). The system alternatively or cumulatively also comprises circuitry (22x) for indicating a potential capability of operational speed of the data path and/or circuitry (24x) for indicating an amount of current leakage of the circuitry for providing data processing functionality. The system also comprises circuitry (26) for adjusting the at least one system parameter in response to either or both of the circuitry for indicating a potential capability and the circuitry for indicating an amount of current leakage.Type: GrantFiled: December 18, 2003Date of Patent: January 9, 2007Assignee: Texas Instruments IncorporatedInventors: Sami Issa, Uming Ko, Baher Haroun, David Scott
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Patent number: 7154810Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.Type: GrantFiled: January 31, 2005Date of Patent: December 26, 2006Assignee: Broadcom CorporationInventors: Gil I. Winograd, Esin Terzioglu, Ali Anvar, Sami Issa
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Publication number: 20060261857Abstract: A single integrated circuit (12). The integrated circuit comprises a first circuit (14x) having a data path, the first circuit consisting of a first number of logic gates for performing a plurality of logic functions. The integrated circuit also comprises a circuit (22x) for indicating a potential speed capability of the data path. The circuit for indicating comprises a second number of logic gates (82, 92) for performing the plurality of logic functions, wherein the second number is less than the first number. The circuit for indicating also comprises additional circuitry (88, 98) for representing parasitic characteristics in the data path.Type: ApplicationFiled: July 11, 2006Publication date: November 23, 2006Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sami Issa, Baher Haroun, Shakti Rath
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Patent number: 7131089Abstract: A computer programmed to specify a design of a circuit for indicating a potential speed capability of a data path in a predetermined circuit. The data path comprises a plurality of logic functions to be performed by a first number of logic gates. The computer specifies the design by steps. In one step, the program specifies a second number of logic gates to be included in the circuit for indicating a potential speed capability. The second number of logic gates is less than the first number of logic gates and provides voltage and delay characteristics comparable to the data path. The computer also specifies additional circuitry to be included in the circuit for indicating a potential speed capability, wherein the additional circuitry is for representing parasitic characteristics in the data path.Type: GrantFiled: December 18, 2003Date of Patent: October 31, 2006Assignee: Texas Instruments IncorporatedInventors: Sami Issa, Baher Haroun, Shakti S. Rath
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Patent number: 7002383Abstract: A method and apparatus are disclosed for efficiently doubling a first frequency of a first clock signal. A second clock signal at a second frequency is generated by dividing the first frequency of the first clock signal by two, such that the second frequency is half of the first frequency and a duty cycle of the second clock signal is 50%. Also, a set of phase-delayed clock signals is generated in response to the second clock signal such that the set of phase-delayed clock signals are delayed in phase with respect to the second clock signal. Further, the set of phase-delayed clock signals is combined to generate a third clock signal at a third frequency, such that the third frequency is twice that of the first frequency and a duty cycle of the third clock signal is 50%.Type: GrantFiled: September 4, 2003Date of Patent: February 21, 2006Assignee: Broadcom CorporationInventors: Sami Issa, Morteza (Cyrus) Afghahi
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Publication number: 20050273742Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability.Type: ApplicationFiled: May 27, 2005Publication date: December 8, 2005Applicant: Texas Instruments IncorporatedInventors: Sami Issa, Uming Ko, David Scott
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Patent number: 6947350Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier. One embodiment of the present invention relates to a memory device comprising a plurality of synchronous controlled global elements and a plurality of self-timed local elements. In this embodiment, at least one of the self-timed local elements interfaces with the synchronous controlled global element.Type: GrantFiled: November 12, 2003Date of Patent: September 20, 2005Assignee: Broadcom CorporationInventors: Gil I. Winograd, Esin Terzioglu, Ali Anvar, Sami Issa
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Publication number: 20050170584Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: ApplicationFiled: March 29, 2005Publication date: August 4, 2005Inventor: Sami Issa
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Publication number: 20050128854Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.Type: ApplicationFiled: January 31, 2005Publication date: June 16, 2005Inventors: Gil Winograd, Esin Terzioglu, Ali Anvar, Sami Issa
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Patent number: 6906946Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: GrantFiled: September 9, 2003Date of Patent: June 14, 2005Assignee: Broadcom CorporatinInventor: Sami Issa
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Patent number: 6898663Abstract: In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows being programmable by a small number of inputs. In another aspect, the invention discloses a mechanism for refreshing all banks or a programmable number of banks simultaneously in a multi-bank memory. In yet another aspect, the present invention describes a mechanism for refreshing a programmable multiple memory rows and a programmable multiple banks simultaneously.Type: GrantFiled: August 12, 2003Date of Patent: May 24, 2005Assignee: Broadcom CorporationInventors: Gil I. Winograd, Sami Issa, Morteza Cyrus Afghahi