Abstract: An apparatus including an array of field-effect transistors, each field-effect transistor including a channel, source and drain electrodes, and a gate electrode configured to enable the flow of electrical current to be varied, the gate electrode separated from the channel by a dielectric material configured to inhibit a flow of electrical current between the channel and gate electrode, wherein the gate electrode of each field-effect transistor is connected in parallel to the gate electrodes of the other field-effect transistors in the array, and wherein a respective two-terminal current-limiting component is coupled to each gate electrode such that, in the event that a defect in the dielectric material of a particular field-effect transistor allows a leakage current to flow between the channel and gate electrode of that field-effect transistor, the respective two-terminal current-limiting component limits the magnitude of the leakage current.

Abstract: A MESFET transistor on a horizontal substrate surface with at least one wiring layer on the substrate surface. The transistor comprises source, drain and gate electrodes which are at least partly covered by a semiconducting channel layer. The source, drain and gate electrodes optionally comprise interface contact materials for changing the junction type between each electrode and the channel. The interface between the source electrode and the channel is an ohmic junction, the interface between the drain electrode and the channel is an ohmic junction, and the interface between the gate electrode and the channel is a Schottky junction. The substrate is a CMOS substrate.

Abstract: A photosensitive field-effect transistor which can be configured to provide an electrical response when illuminated by electromagnetic radiation incident on the transistor. The field-effect transistor has a channel (13) made from a two-dimensional material and comprises a photoactive layer (22) which can be configured to donate charge carriers to the transistor channel (13) when electromagnetic radiation is absorbed in the photoactive layer (22). The photosensitive field-effect transistor comprises a top electrode (21) which is in contact with the photoactive layer on one or more contact areas which together form a contact pattern. With a suitably patterned top electrode (21), a voltage applied to the electrode can function as an electrical shutter which can switch the photosensitive field-effect transistor between a light-sensitive state and a light-immune state.

Abstract: A photosensitive field-effect transistor comprising a substrate with a source electrode, a drain electrode and a gate electrode. The transistor comprises a photoactive layer which at least partly covers the gate electrode, and a channel layer which covers the photoactive layer and at least partly covers both the source electrode and the drain electrode. The channel layer comprises a two-dimensional material whose conductivity is modulated by charge carriers transferred from the photoactive layer when electromagnetic radiation is absorbed in the photoactive layer.

Abstract: An apparatus including an array of field-effect transistors, each field-effect transistor including a channel, source and drain electrodes, and a gate electrode configured to enable the flow of electrical current to be varied, the gate electrode separated from the channel by a dielectric material configured to inhibit a flow of electrical current between the channel and gate electrode, wherein the gate electrode of each field-effect transistor is connected in parallel to the gate electrodes of the other field-effect transistors in the array, and wherein a respective two-terminal current-limiting component is coupled to each gate electrode such that, in the event that a defect in the dielectric material of a particular field-effect transistor allows a leakage current to flow between the channel and gate electrode of that field-effect transistor, the respective two-terminal current-limiting component limits the magnitude of the leakage current.

Abstract: A photosensitive field-effect transistor which can be configured to provide an electrical response when illuminated by electromagnetic radiation incident on the transistor. The field-effect transistor has a channel (13) made from a two-dimensional material and comprises a photoactive layer (22) which can be configured to donate charge carriers to the transistor channel (13) when electromagnetic radiation is absorbed in the photoactive layer (22). The photosensitive field-effect transistor comprises a top electrode (21) which is in contact with the photoactive layer on one or more contact areas which together form a contact pattern. With a suitably patterned top electrode (21), a voltage applied to the electrode can function as an electrical shutter which can switch the photosensitive field-effect transistor between a light-sensitive state and a light-immune state.

Abstract: A photosensitive field-effect transistor comprising a substrate with a source electrode, a drain electrode and a gate electrode. The transistor comprises a photoactive layer which at least partly covers the gate electrode, and a channel layer which covers the photoactive layer and at least partly covers both the source electrode and the drain electrode. The channel layer comprises a two-dimensional material whose conductivity is modulated by charge carriers transferred from the photoactive layer when electromagnetic radiation is absorbed in the photoactive layer.

Abstract: An apparatus and method, the apparatus including a plurality of sensors; readout circuitry configured to read information from each of the plurality of sensors; and wherein the apparatus has identifier information and calibration information stored with the identifier information and the apparatus is configured to be coupled to at least one other apparatus to form an array of apparatus.

Abstract: A method and apparatus wherein the method comprises: providing at least one electrode within a semiconductor layer wherein the semiconductor layer is provided on a first side of a wafer; thinning the wafer to produce a thinned wafer; providing graphene on a second side of the thinned wafer; attaching the semiconductor layer to an electrical interface on the first side of the thinned wafer; and providing at least one electrical connection from the graphene to the electrical interface so as to form a transistor comprising the at least one electrode and the graphene.

Abstract: An apparatus, including a quantum dot graphene field effect transistor configured to operate such that photons incident thereon cause electron-hole pairs to be formed; a connector element connected to the back gate of the transistor; a switch element as an output switch to provide an output for a current flowing through the transistor. The transistor is configured to be back gate biased via the connector element connected to the back gate such that the electrons or the holes formed are trapped in an at least one quantum dot and respectively the holes or the electrons migrate to the channel of the transistor. A drain to source voltage connected to the transistor causes a current proportional to the charge of the holes or electrons trapped at the quantum dots by the electrons or holes to flow in the channel.

Abstract: An apparatus comprising at least one pair of a first inner and second outer photodetector, each photodetector comprising a channel member, respective source and drain electrodes configured to enable a flow of electrical current through the channel member between the source and drain electrodes, and a plurality of quantum dots configured to generate electron-hole pairs on exposure to incident electromagnetic radiation to produce a detectable change in the electrical current flowing through the channel member. The first inner and second outer photodetectors are configured to generate electron-hole pairs which produce an increase and decrease in electrical current through the channel members. The first inner and the second outer photodetectors share a common channel member, which is partitioned by one or more of the respective source and drain electrodes respectively extending in two dimensions such that the first inner photodetector is defined within the second outer photodetector.

Abstract: A MESFET transistor on a horizontal substrate surface with at least one wiring layer on the substrate surface. The transistor comprises source, drain and gate electrodes which are at least partly covered by a semiconducting channel layer. The source, drain and gate electrodes optionally comprise interface contact materials for changing the junction type between each electrode and the channel. The interface between the source electrode and the channel is an ohmic junction, the interface between the drain electrode and the channel is an ohmic junction, and the interface between the gate electrode and the channel is a Schottky junction. The substrate is a CMOS substrate.

Abstract: An apparatus and method, the apparatus including a plurality of sensors; readout circuitry configured to read information from each of the plurality of sensors; and wherein the apparatus has identifier information and calibration information stored with the identifier information and the apparatus is configured to be coupled to at least one other apparatus to form an array of apparatus.

Abstract: An apparatus comprising at least one pair of a first inner and second outer photodetector, each photodetector comprising a channel member, respective source and drain electrodes configured to enable a flow of electrical current through the channel member between the source and drain electrodes, and a plurality of quantum dots configured to generate electron-hole pairs on exposure to incident electromagnetic radiation to produce a detectable change in the electrical current flowing through the channel member. The first inner and second outer photodetectors are configured to generate electron-hole pairs which produce an increase and decrease in electrical current through the channel members. The first inner and the second outer photodetectors share a common channel member, which is partitioned by one or more of the respective source and drain electrodes respectively extending in two dimensions such that the first inner photodetector is defined within the second outer photodetector.

Abstract: A method and apparatus wherein the method comprises: providing at least one electrode within a semiconductor layer wherein the semiconductor layer is provided on a first side of a wafer; thinning the wafer to produce a thinned wafer; providing graphene on a second side of the thinned wafer; attaching the semiconductor layer to an electrical interface on the first side of the thinned wafer; and providing at least one electrical connection from the graphene to the electrical interface so as to form a transistor comprising the at least one electrode and the graphene.

Abstract: An apparatus, including a quantum dot graphene field effect transistor configured to operate such that photons incident thereon cause electron-hole pairs to be formed; a connector element connected to the back gate of the transistor; a switch element as an output switch to provide an output for a current flowing through the transistor. The transistor is configured to be back gate biased via the connector element connected to the back gate such that the electrons or the holes formed are trapped in an at least one quantum dot and respectively the holes or the electrons migrate to the channel of the transistor. A drain to source voltage connected to the transistor causes a current proportional to the charge of the holes or electrons trapped at the quantum dots by the electrons or holes to flow in the channel.

Abstract: A delay locked loop comprises a delay line having a plurality of sequentially connected delay elements (E1 to E16). The delay line has an input for receiving an input signal and an output for outputting an output signal. A phase detector (6) is configured to detect a phase difference between the input signal and the output signal, and to generate a control signal based on said difference for supply to at least a part of the delay line. At least one further delay element (EO, E17). One of said at least one further delay element may be further configured to receive said control signal. A clock multiplier (4) can include such a delay locked loop.

Abstract: Method and apparatus for reducing power in a switched capacitor circuit. In one embodiment, the power reduction apparatus includes a detector connected to both inputs of an operational amplifier in a switched capacitor circuit, and a controller. The detector monitors the inputs. A voltage corresponding to full settling (i.e. a zero difference between the inputs) is stored. The voltage corresponding to the difference between the inputs is compared to the previous value to determine whether it is within the desired range. The controller is connected to an output signal of the detector. The controller adjusts a bias current of the operational amplifier based on the output signal to as low as possible but just above a value where the comparison falls outside the desired range. The power consumption of the operational amplifier is minimized while a settling time of the operational amplifier is still adequate for maximum performance.