Patents by Inventor Sami NURMI

Sami NURMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079350
    Abstract: A packaging arrangement is provided that suppresses stress induced by extreme temperature changes during the process of attaching the electronic component. The arrangement includes adding to the package columnar conductors embedded in a solid support substance.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 7, 2024
    Inventors: Shigeru ENDO, Sami NURMI
  • Publication number: 20230360945
    Abstract: An electronic component is provided that includes a first die, a support with a die-attachment surface and a die-aligning element that is adjacent to the die-attachment surface. The die aligning element includes a first die-alignment wall. Moreover, a first side of the first die is horizontally fixed to the first die-alignment wall with a die-attach material. The side of the first die that is opposite to the first side of the first die is horizontally unfixed.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 9, 2023
    Inventors: Sami NURMI, Teppo SYRJÄNEN
  • Patent number: 11527497
    Abstract: An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 13, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Heikki Kuisma, Sami Nurmi
  • Publication number: 20190177159
    Abstract: A semiconductor assembly includes a semiconductor package. An essentially planar portion of a die attach paddle is disposed above a semiconductor die. The planar portion forms a plane of the paddle. The area of the planar portion is greater than a combined area of an orthogonal projection of the die on the plane of the paddle. The planar portion is coupled via bond pads to first leads of the lead-frame. The first leads are configured to be coupled to a ground potential so that the planar portion forms a first ground plane inside the semiconductor package above the die. A second ground plane is disposed on the face of the printed circuit board that resides towards the semiconductor package. The second ground plane is coplanar with the plane of the paddle, and disposed under the body of the semiconductor package.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 13, 2019
    Inventors: Kimmo KAIJA, Sami NURMI, Santeri TUOMIKOSKI, Hristo BRACHKOV
  • Publication number: 20190112185
    Abstract: A MEMS component package comprises a body having outer surfaces of non-conductive material and a plurality of conducting leads protruding therefrom. A solder pad is applied on a blind pad exposed on a PCB surface while applying solder paste. The blind pad is collocated with an intended location of the body, and the solder pad is collocated with the blind pad. The package is placed on the PCB surface, joining the leads to the pin pads of the PCB with solder paste. The PCB is heated to melt the paste. This couples the leads to the pin pads, and melts the solder pad. The melting transforms the solder pad into a solder bump configured to couple the body to the at least one blind pad. The solder bump attaches with a non-galvanic contact directly to the non-conductive plastic bottom of the body.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 18, 2019
    Inventors: Nikolai MANTYOJA, Kimmo KAIJA, Sami NURMI, Jukka ESKELINEN
  • Patent number: 9828239
    Abstract: A method of making a system-in-package device, and a system-in-package device is disclosed. In the method, at least one first species die with predetermined dimensions, at least one second species die with predetermined dimensions, and at least one further component of the system-in-device is included in the system-in package device. At least one of the first and second species dies is selected for redimensioning, and material is added to at least one side of the selected die such that the added material and the selected die form a redimensioned die structure. A connecting layer is formed on the redimensioned die structure. The redimensioned die structure is dimensioned to allow mounting of the non-selected die and the at least one further component into contact with the redimensioned die structure via the connecting layer.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: November 28, 2017
    Assignee: MURATA ELECTRONICS OY
    Inventors: Heikki Kuisma, Sami Nurmi
  • Patent number: 9663352
    Abstract: A microelectromechanical device that comprises a wafer plate, a group of one or more wafer connector elements, and an electrical distribution layer between them. For reduced device thickness, the wafer plate comprises at least two dies and bonding material that bonds the at least two dies alongside each other to the longitudinal extent of the wafer plate, wherein at least one of the dies is a microelectromechanical die. The electrical distribution layer covers the wafer plate and includes a layer of dielectric material and a layer of conductive material, wherein the layer of conductive material is patterned within the layer of dielectric material for electrical interconnection of the dies and the wafer connector elements. With the new configuration, significantly reduced MEMS device thicknesses are achieved.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: May 30, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Heikki Kuisma, Sami Nurmi
  • Publication number: 20140332910
    Abstract: A microelectromechanical device that comprises a wafer plate, a group of one or more wafer connector elements, and an electrical distribution layer between them. For reduced device thickness, the wafer plate comprises at least two dies and bonding material that bonds the at least two dies alongside each other to the longitudinal extent of the wafer plate, wherein at least one of the dies is a microelectromechanical die. The electrical distribution layer covers the wafer plate and includes a layer of dielectric material and a layer of conductive material, wherein the layer of conductive material is patterned within the layer of dielectric material for electrical interconnection of the dies and the wafer connector elements.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 13, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Heikki KUISMA, Sami NURMI