Patents by Inventor Samie Samaan

Samie Samaan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-linear control for voltage regulator
    Patent number: 9696350
    Abstract: Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Edward A. Burton, Gerhard Schrom, Michael W. Rogers, Alexander Lyakhov, Ravi Sankar Vunnam, Jonathan P. Douglas, Fabrice Paillet, J. Keith Hodgson, William Dawson Kesling, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan, Samie Samaan, George Geannopoulos
  • Determination of cache entry for future operation
    Publication number: 20060230228
    Abstract: A system may include M cache entries, each of the M cache entries to transmit a signal indicating a read from or a write to the cache entry and comprising a data register and a memory address register, and K layers of decision cells, where K=log2M. The K layers M/2 decision cells of a first layer to indicate the other one of the respective two of the M cache entries and to transmit a hit signal in response to the signal, a second layer of M/4 decision cells to enable the other one of the respective two of the M/2 decision cells of the first layer and transmit a second hit signal in response to the signal, a (K-1)th layer of two decision cells to enable the other one of the respective two decision cells of the (K-2)th layer and transmit a third hit signal in response to the second hit signal, and a Kth layer of a root decision cell to enable the other one of the respective two decision cells of the (K-1)th layer in response to the third hit signal.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 12, 2006
    Inventors: Samie Samaan, Avinash Sodani
  • Register alias table cache
    Publication number: 20050138338
    Abstract: Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements.
    Type: Application
    Filed: December 18, 2003
    Publication date: June 23, 2005
    Inventors: Avinash Sodani, Stephan Jourdan, Samie Samaan
  • Register file cache
    Publication number: 20050138297
    Abstract: Embodiments of the present invention relate to a system and method for associating a register file cache with a register file in a computer processor.
    Type: Application
    Filed: December 23, 2003
    Publication date: June 23, 2005
    Inventors: Avinash Sodani, Per Hammarlund, Samie Samaan, Kurt Kreitzer, Tom Fletcher