Abstract: Embodiments of data recovery apparatus include oscillators, edge detection circuitry, and data storage. The oscillators generate data detection signals, which convey first series of pulses during time periods for which a serial bit stream conveys a logical 1, and second series of pulses during time periods for which the serial bit stream conveys a logical 0. The edge detection circuitry detects transition edges of the first and second series of pulses, and generates data storage signals that include first indications of detected transition edges in the first series of pulses and second indications of detected transition edges in the second series of pulses. In response to receiving a first indication, a logical 1 is written into an unmasked subset of data storage bit locations. In response to receiving a second indication, a logical 0 is written into the unmasked subset of bit locations.

Abstract: A data recovery circuit includes a pulse width indicator circuit, an edge detection circuit and a first storage. The pulse width indicator circuit is configured to receive, at an input, a data stream and provide pulses, at respective outputs, that are indicative of respective data bits in the received data stream. The edge detection circuit is configured to receive, on respective inputs, the pulses from the pulse width indicator circuit and provide respective storage signals, on respective outputs that are indicative of a logic level of the respective data bits, responsive to the pulses. The first storage is configured to receive and store the respective storage signals.

Abstract: An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.

Abstract: Techniques and technologies are provided for compressing differential samples of bandwidth-limited data and coding the compressed differential samples to reduce bandwidth and power consumption when communicating bandwidth-limited data over a serial interface which couples one integrated circuit to another integrated circuit.

Abstract: Embodiments of data recovery apparatus include oscillators, edge detection circuitry, and data storage. The oscillators generate data detection signals, which convey first series of pulses during time periods for which a serial bit stream conveys a logical 1, and second series of pulses during time periods for which the serial bit stream conveys a logical 0. The edge detection circuitry detects transition edges of the first and second series of pulses, and generates data storage signals that include first indications of detected transition edges in the first series of pulses and second indications of detected transition edges in the second series of pulses. In response to receiving a first indication, a logical 1 is written into an unmasked subset of data storage bit locations. In response to receiving a second indication, a logical 0 is written into the unmasked subset of bit locations.

Abstract: A data recovery circuit includes a pulse width indicator circuit, an edge detection circuit and a first storage. The pulse width indicator circuit is configured to receive, at an input, a data stream and provide pulses, at respective outputs, that are indicative of respective data bits in the received data stream. The edge detection circuit is configured to receive, on respective inputs, the pulses from the pulse width indicator circuit and provide respective storage signals, on respective outputs that are indicative of a logic level of the respective data bits, responsive to the pulses. The first storage is configured to receive and store the respective storage signals.

Abstract: Techniques and technologies are provided for compressing differential samples of bandwidth-limited data and coding the compressed differential samples to reduce bandwidth and power consumption when communicating bandwidth-limited data over a serial interface which couples one integrated circuit to another integrated circuit.

Abstract: An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.