Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source latches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: A single, common correlation filter (CF) core is provided in a receiver for recovery of data from received code division multiple access (CDMA) signals. Signals are received over CDMA channels with different data rates, where the received signals include user information such as pilot and data symbols that have been spread according to different despreading rates including tier 1, tier 2 and tier 3 rates, where tier 1 is the smallest despreading rate. The received signal is correlated at the smallest despreading rate in the correlation filter (CF) by time multiplexing delayed versions of the pseudorandom noise (PN) code. The correlated information is then demultiplexed and pilot-aided QPSK demodulated. The demodulated information is summed at the proper integer multiple of the tier 1 rate to achieve tier 2 and tier 3 despreading rates. According to an embodiment, the three strongest multipaths components in terms of the received power are selected in a window or time period for optimal information recovery.

Abstract: A single, common correlation filter (CF) core is provided in a wireless system using CDMA. A plurality of channels with different data rates are provided in the wireless system. The channels provided in the wireless system include the access channel, the maintenance channel, and the traffic channel in which information (e.g., pilot or data symbols or both) is transmitted at the tier 1, tier 2 and tier 3 rates. The data rate for transmitting the information is programmable by digital signal processor (DSP). A user-unique code, such as a PN code, is applied to the information being transmitted in the channels of the wireless system. The information is QPSK modulated and transmitted in any one of the channels at any data rate. The transmitted information is correlated at the smallest data rate (i.e., the tier 1 rate) in the correlation filter (CF) of the wireless system by time multiplexing delayed versions of the PN code to the correlation filter core.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: A single, common correlation filter (CF) core is provided in a wireless system using CDMA. A plurality of channels with different data rates are provided in the wireless system. The channels provided in the wireless system include the access channel, the maintenance channel, and the traffic channel in which information (e.g., pilot or data symbols or both) is transmitted at the tier 1, tier 2 and tier 3 rates. The data rate for transmitting the information is programmable by digital signal processor (DSP). A user-unique code, such as a PN code, is applied to the information being transmitted in the channels of the wireless system. The information is QPSK modulated and transmitted in any one of the channels at any data rate. The transmitted information is correlated at the smallest data rate (i.e., the tier 1 rate) in the correlation filter (CF) of the wireless system by time multiplexing delayed versions of the PN code to the correlation filter core.

Abstract: To check hardware logic, one can duplicate the logic and compare the results from identical circuits. One can also use a check sum technique that predicts the check sum for the expected result and compare it against the check sum of the actual result produced by the hardware circuits. The present invention employs this technique for hardware which performs modular reduction operations which compute (A mod N) which is the calculation of the remainder of A divided by N, which can be expressed as B=N−AQ for some quotient Q. When R is the integer used as the modulus for the check sum, the check sum approach predicts the check sum of the remainder, that is, the check sum of (N−AQ) mod R. If C(x)=x mod R is the check sum of x, the predicted check sum is C(N−AQ)=(C(N)−C(A)C(Q)) mod R. Thus, a multiplier is normally required to calculate the predicted check sum.

Abstract: A tonal adjusting device for selectively changing the pitch of one or more strings of a guitar. The tonal adjusting device includes a lever assembly with upper and lower arms that are designed for being positioned around the neck of a stringed instrument. The upper arm has dampening members for selectively engaging the strings when the upper arm engages the face of the neck of the instrument.

Abstract: A single, common correlation filter (CF) core is provided in a wireless system using CDMA. A plurality of channels with different data rates are provided in the wireless system. The channels provided in the wireless system include the access channel, the maintenance channel, and the traffic channel in which information (e.g., pilot or data symbols or both) is transmitted at the tier 1, tier 2 and tier 3 rates. The data rate for transmitting the information is programmable by digital signal processor (DSP). A user-unique code, such as a PN code, is applied to the information being transmitted in the channels of the wireless system. The information is QPSK modulated and transmitted in any one of the channels at any data rate. The transmitted information is correlated at the smallest data rate (i.e., the tier 1 rate) in the correlation filter (CF) of the wireless system by time multiplexing delayed versions of the PN code to the correlation filter core.