Abstract: Frequency differences between differing clock sources are compensated for by an adaptive filtering mechanism. An amount of frequency drift between two clock sources is determined. Then, based on that amount of frequency drift, a filtering value is selected to be used in tracking the frequency drift. If the frequency drift is determined to be large, then a minimum filtering value is selected. However, if it is determined to be small, then a maximum filtering value is selected. The selected filtering value is used to adjust the address(es) of one or more data bits being transmitted and received using the two clock sources, such that the frequency drift is properly tracked.

Abstract: Frequency differences between differing clock sources are compensated for by an adaptive filtering mechanism. An amount of frequency drift between two clock sources is determined. Then, based on that amount of frequency drift, a filtering value is selected to be used in tracking the frequency drift. If the frequency drift is determined to be large, then a minimum filtering value is selected. However, if it is determined to be small, then a maximum filtering value is selected. The selected filtering value is used to adjust the address(es) of one or more data bits being transmitted and received using the two clock sources, such that the frequency drift is properly tracked.

Abstract: A serial data stream is recovered using a local clock, which is asynchronous to the clock used to transmit the serial data. The incoming serial data stream is phase shifted or delayed by a digital phase-locked loop so that it may be reliably sampled by the local clock. The DPLL samples the serial data stream and captures data on both the rising and falling edges of the local clock employing three edge detectors. This partitions the data stream into two bit samples, which the DPLL presents to a deserializer. The deserializer converts the serial data to parallel data and assembles the received data back into data bytes. The deserializer also generates a received byte clock used for presenting the parallel data to, for example, the ESCON channel logic.