Abstract: The present disclosure relates to a FET device (10), comprising a substrate (11), a GaN structure (15) covering a portion of the substrate (11), and a gate metal layer (17) on top of the GaN structure (15). The GaN structure (15) comprises at least one first section having a first height, and a second section having a second height that is smaller than the first height, wherein a first interface (41) between the at least one first section of the GaN structure (15) and the gate metal layer (17) has ohmic contact properties, and wherein a second interface (43) between the second section of the GaN structure (15) and the gate metal layer (17) has non-ohmic contact properties.

Abstract: The present disclosure relates to a FET device (10), comprising a substrate (11), a GaN structure (15) covering a portion of the substrate (11), and a gate metal layer (17) on top of the GaN structure (15).

Abstract: A semiconductor device includes a die layer comprising a main surface. A plurality of first terminals are mounted on the main surface of the die layer, the first terminals forming a grid of unit cells with hexagon contours arranged side-by-side across the main surface of the die layer. A plurality of second terminals are mounted on the main surface of the die layer, each second terminal forming a hexagon contour arranged within a unit cell of a respective first terminal. A plurality of third terminals is mounted on the main surface of the die layer, each third terminal formed as a hexagon and arranged within the hexagon contour of a respective second terminal. At least two metallization layers are arranged over the plurality of first, second and third terminals and are configured to receive electrical currents from the plurality of first, second and third terminals.

Abstract: An electronic device including a die including a diode including a semiconductor base material that includes a Group 14 element and a high electron mobility transistor over the semiconductor layer, wherein the high electron mobility transistor is coupled to the diode. In an embodiment, the die can include an insulating layer under the semiconductor layer. In another embodiment, the diode can be a lateral diode. In still another embodiment, the die can include an isolation region that isolates cathode or anode electrode of the diode from each of the current-carrying electrodes of the high electron mobility transistor. In a further embodiment, the die can include an electrical connection that is configured so that the diode is in a blocking state when the high electron transistor is in a conducting state, and the diode is in a conducting state when the high electron transistor is in a blocking state.

Abstract: An electronic device can include a HEMT that includes a channel layer, a barrier layer, and a gate electrode. The barrier layer can be disposed between the channel layer and the gate electrode and include a first portion, a second portion, and a third portion. The second portion can be spaced apart from the channel layer by the first portion, and the second portion is spaced apart from the gate electrode by the third portion. The second portion of the barrier layer can be configured to trap more charge, more readily recombine electrons and holes, or both as compared to each of the first and third portions of the barrier layer. The HEMT can have a VTH of at least 2 V and a subthreshold slope of at most 50 mV/decade of IDS.

Abstract: A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region.

Abstract: A semiconductor device includes a charge-compensating region with a first structure disposed adjoining an end portion of the charge-compensating region. The first structure is configured to reduce charge-imbalances present in the charge-compensating region. In one embodiment, the first structure includes a trench that extends along the vertical depth of the charge-compensated trench so that the final charge-compensating region is provided without corner portions. In one embodiment, a material, such as a dielectric material and/or a polycrystalline semiconductor material, may be disposed within the trench and at least along the end portion of the charge-compensating region. Among other things, the first structure improves device electrical performance and manufacturing yields.

Abstract: A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region.