Patents by Inventor Samir Narayan Hulyalkar

Samir Narayan Hulyalkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110001873
    Abstract: A frame rate converter device and method for interpolation during frame rate conversion are disclosed. The method includes, receiving input frames containing film content and video content. The film content exhibits a 3:2 pull-down cadence while video content that does not exhibit such cadence. Consecutive frames Cn and Cn+1 are interpolated to form Fn using the frame rate converter. The frame rate converter further selects as an output frame, either current or previous ones of interpolated frames or input frames. The selection is made so as to reduce both film judder and video judder. The invention is suitable for use on video input frames at 60 frames per second (fps) derived from a 24 fps cinema using 3:2 pull-down, and also blended with 60 Hz overlay video such as subtitle text. The invention can be used to obtain a good overall reduction in both overlay video judder and film judder.
    Type: Application
    Filed: March 19, 2010
    Publication date: January 6, 2011
    Inventors: Daniel Doswald, Michael Joseph Erwin, Samir Narayan Hulyalkar
  • Patent number: 6141384
    Abstract: In the standard format now adapted by FCC for a digital HDTV signal, the video data symbols are interleaved and trellis encoded in accordance with a 4-state trellis code and the interleaving is of sequences of every 12 successive symbols. At the receiver the trellis decoder is therefore projected to consist of 12 respective decoder stages for the 12 interleaved sequences, each decoder stage having a branch metric calculator unit (BMC), an add-compare-select (ACS) unit and a path memory unit (PMU). The present invention separates the path memory requirements for the 12 interleaved sequences from the requisite BMC and ACS functions, so that the latter two units can provide those functions for all of the 12 interleaved sequences. A single extended PMU provides for storage of pointers to possible predecessor states of the trellis code corresponding to a present state thereof, going back to a predetermined number (such as 16) of sequentially preceding received symbol values.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: October 31, 2000
    Assignee: Philips Electronics North America Corporation
    Inventors: Karl Raymond Wittig, Samir Narayan Hulyalkar