Abstract: According to one embodiment, a current-mode driver provides pre-emphasis for a transmitter. The current-mode driver includes a filtering circuit comprising a resistor, an inductor, and a capacitor. The filtering circuit is operable to receive a data signal and produce a filtered data signal. The filtering circuit may be tuned to produce a ringing frequency with an underdamped transient decay in the filtered data signal that compensates for signal degradation caused by the optical transmitter. The current-mode driver may also include a current source coupled to the filtering circuit. The current source may be operable to generate a compensation signal based on the filtered data signal that is capable of driving the transmitter.

Abstract: A container includes a receptacle having a sidewall with inner and outer surfaces and a rim. The container lid has inner and outer surfaces, a central portion, and a periphery divided into a first periphery portion and a second periphery portion extending outward and downward from the first periphery portion. In a first mounting configuration, the central and first periphery portions of the lid are nested below the receptacle rim with the lid outer surface contacting the receptacle sidewall inner surface. In a second mounting configuration, the lid is inverted and the second periphery portion extends over the rim of the receptacle, while the first periphery and central portions of the lid extend above the receptacle rim, and the inner surface of the lid contacts the outer surface of the receptacle wall. A second, identical receptacle can be included, with both receptacles mounted to opposing sides of the lid.

Abstract: According to one embodiment of the present disclosure, a current-mode driver with built-in CTLE provides signal correction for a transmitter. The current-mode driver includes a digital current source operable to use a data signal to produce a main current signal. The current-mode driver also includes a filtering circuit comprising a resistor and a capacitor. The filtering circuit is operable to receive a negative data signal and produce a filtered data signal. The filtering circuit may be tuned to produce a zero at a pole frequency in the filtered data signal that compensates for signal degradation caused by the optical transmitter. The current-mode driver also includes an analog current source coupled in parallel to the digital current source, wherein the analog current source is operable to generate a subtraction current signal proportional to the filtered data signal. The subtraction current signal combined with the main current signal are operable to drive the transmitter.

Abstract: According to one embodiment, a current-mode driver provides pre-emphasis for a transmitter. The current-mode driver includes a filtering circuit comprising a resistor, an inductor, and a capacitor. The filtering circuit is operable to receive a data signal and produce a filtered data signal. The filtering circuit may be tuned to produce a ringing frequency with an underdamped transient decay in the filtered data signal that compensates for signal degradation caused by the optical transmitter. The current-mode driver may also include a current source coupled to the filtering circuit. The current source may be operable to generate a compensation signal based on the filtered data signal that is capable of driving the transmitter.

Abstract: According to one embodiment of the present disclosure, a current-mode driver with built-in CTLE provides signal correction for a transmitter. The current-mode driver includes a digital current source operable to use a data signal to produce a main current signal. The current-mode driver also includes a filtering circuit comprising a resistor and a capacitor. The filtering circuit is operable to receive a negative data signal and produce a filtered data signal. The filtering circuit may be tuned to produce a zero at a pole frequency in the filtered data signal that compensates for signal degradation caused by the optical transmitter. The current-mode driver also includes an analog current source coupled in parallel to the digital current source, wherein the analog current source is operable to generate a subtraction current signal proportional to the filtered data signal. The subtraction current signal combined with the main current signal are operable to drive the transmitter.

Abstract: A circuit may include a delay element, a voltage adjust line, and a controllable capacitance. The delay element may have a delay and may include an input and an output. The input may be coupled to the output. The voltage adjust line may be configured to provide an adjusting voltage to the delay element to adjust the delay of the delay element. The controllable capacitance may be coupled to the output of the delay element and may be configured such that a change of the controllable capacitance adjusts the delay of the delay element.

Abstract: A transmitter may include a first path configured to receive a signal, to attenuate the low frequency components of the signal, and to output the low frequency component attenuated signal. The transmitter may further include a second path configured to receive the signal, to amplify the signal, and to output the amplified signal. The transmitter may also include a node coupled to the first path and the second path and configured such that the low frequency component attenuated signal and the amplified signal combine at the node.

Abstract: A circuit may include a low-dropout (LDO) voltage regulator. The LDO voltage regulator may include an output coupled to a supply of a load circuit. The LDO voltage regulator may be configured to provide a supply voltage to the load circuit. The circuit may also include a current source coupled to the supply of the load circuit and the output of the LDO voltage regulator. The current source may be configured to supply current to the load circuit in a manner that reduces current supplied to the load circuit by the LDO voltage regulator.

Abstract: A circuit may include a delay element, a voltage adjust line, and a controllable capacitance. The delay element may have a delay and may include an input and an output. The input may be coupled to the output. The voltage adjust line may be configured to provide an adjusting voltage to the delay element to adjust the delay of the delay element. The controllable capacitance may be coupled to the output of the delay element and may be configured such that a change of the controllable capacitance adjusts the delay of the delay element.

Abstract: According to an aspect of an embodiment of the present disclosure, a method of relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data includes adding an ISI cancellation value to input data received at a first clock rate to generate first speculative data. The method further includes subtracting the ISI cancellation value from the input data to generate second speculative data. The method also includes sampling the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed.

Abstract: A transmitter may include a first path configured to receive a signal, to attenuate the low frequency components of the signal, and to output the low frequency component attenuated signal. The transmitter may further include a second path configured to receive the signal, to amplify the signal, and to output the amplified signal. The transmitter may also include a node coupled to the first path and the second path and configured such that the low frequency component attenuated signal and the amplified signal combine at the node.

Abstract: According to an aspect of an embodiment of the present disclosure, a method of relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data includes adding an ISI cancellation value to input data received at a first clock rate to generate first speculative data. The method further includes subtracting the ISI cancellation value from the input data to generate second speculative data. The method also includes sampling the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed.

Abstract: Systems and methods are provided for facilitating variable precision tuning of an amplifier circuit. In accordance with one aspect of the present disclosure, the system includes an amplifier having multiple tuning stages to set the gain of the amplifier to discrete gain levels. In particular embodiments, the tuning stages are connected in series and each of the tuning stages includes a resistor connected in parallel to a switch, which can be disengaged to cause the amplifier to set the gain to an adjacent gain level. In certain embodiments, the difference in gain between each adjacent one of the plurality of gain levels is more at higher gain levels than at lower gain levels.

Abstract: In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.

Abstract: In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.

Abstract: Systems and methods are provided for facilitating variable precision tuning of an amplifier circuit. In accordance with one aspect of the present disclosure, the system includes an amplifier having multiple tuning stages to set the gain of the amplifier to discrete gain levels. In particular embodiments, the tuning stages are connected in series and each of the tuning stages includes a resistor connected in parallel to a switch, which can be disengaged to cause the amplifier to set the gain to an adjacent gain level. In certain embodiments, the difference in gain between each adjacent one of the plurality of gain levels is more at higher gain levels than at lower gain levels.

Abstract: In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.

Abstract: In one embodiment, a method can include: receiving a packet in a device; classifying the received packet as a first packet type or a second packet type; when the packet is the first packet type, forwarding the packet to a next hop; and when the packet is the second packet type: performing forward error correction (FEC) encoding on the packet to generate repair data, modifying the packet by adding a multi-protocol label switching (MPLS) header to indicate that the packet is to be forwarded on an FEC-protected label switched path (LSP), generating an additional MPLS packet carrying the repair data, and forwarding the modified packet and the additional packet to a next hop.

Abstract: In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.

Abstract: In one embodiment, a method can include: receiving a packet in a device; classifying the received packet as a first packet type or a second packet type; when the packet is the first packet type, forwarding the packet to a next hop; and when the packet is the second packet type: performing forward error correction (FEC) encoding on the packet to generate repair data, modifying the packet by adding a multi-protocol label switching (MPLS) header to indicate that the packet is to be forwarded on an FEC-protected label switched path (LSP), generating an additional MPLS packet carrying the repair data, and forwarding the modified packet and the additional packet to a next hop.