Abstract: An aspect of the disclosure relates to a method of reducing a third-order intermodulation component at a first terminal of a transistor, including: receiving an input radio frequency (RF) signal cycling with a first frequency at a control terminal of the transistor; generating a feedback RF signal cycling at a second frequency at a second terminal of the transistor, wherein the second frequency is substantially twice the first frequency; and generating a third-order intermodulation cancellation component at the first terminal including combining the input RF signal with the feedback RF signal, wherein the third-order intermodulation cancellation component has a magnitude and phase substantially equal to and opposite a magnitude and phase of the third-order intermodulation component at the first terminal of the transistor, respectively.

Abstract: An amplifier circuit includes an amplifier core having a cascode transistor and a gain transistor, a bias circuit coupled to the amplifier core, the bias circuit comprising: a first current source, a second current source, an operational transconductance amplifier (OTA), a bias cascode transistor pair having a bias cascode transistor and a bias gain transistor, and a replica circuit coupled to the first current source and to the second current source.

Abstract: An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.

Abstract: An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.