Patents by Inventor Samit Chaudhuri

Samit Chaudhuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for automatic clock gating to save power
    Patent number: 7930673
    Abstract: A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: April 19, 2011
    Assignee: Magma Design Automation, Inc.
    Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri
  • Method for optimized automatic clock gating
    Patent number: 7882461
    Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: February 1, 2011
    Assignee: Magma Design Automation, Inc.
    Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri
  • Structured Placement For Bit Slices
    Publication number: 20100011324
    Abstract: Techniques are disclosed for improving bit slice placement and wiring. Some embodiments include swapping cells to improve routing. An alternative embodiment includes copying wiring from a first bit slice to a second bit slice. Another embodiment includes copying blocks or cells from a first bit slice to a second bit slice. Further, the wiring from the first bit slice may be copied to the second bit slice.
    Type: Application
    Filed: June 5, 2009
    Publication date: January 14, 2010
    Inventors: Darren Faulkner, Alan Cheuk-Ming Lam, Samit Chaudhuri, Aditya Shiledar
  • Method For Optimized Automatic Clock Gating
    Publication number: 20080301594
    Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicant: Magma Design Automation, Inc.
    Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri
  • Method For Automatic Clock Gating To Save Power
    Publication number: 20080301593
    Abstract: A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicant: Magma Design Automation, Inc.
    Inventors: Yunjian (William) Jiang, Arvind Srinivasan, Joy Banerjee, Yinghua Li, Partha Das, Samit Chaudhuri