Abstract: A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

Abstract: A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

Abstract: Certain aspects of the present disclosure generally relate to a fin-slab field-effect transistor (FET). For example, certain aspects provide a semiconductor device having a substrate, a well region disposed above the substrate, a first fin disposed above the first well region, and a second fin disposed above the first well region and adjacent to the first fin. In certain aspects, a dielectric region is disposed between the second fin and the first well region, and a first gate region is disposed adjacent to the first fin and the second fin.

Abstract: An integrated circuit test structure has a first set of unit cells in a first conductive layer. The first set of unit cells has a first portion to receive a charge of a first polarity and a second portion to receive a charge of a second polarity. The first portion is electrically independent of the second portion. The first portion has branched conductive lines interdigitated with branched conductive lines of the second portion. The integrated circuit test structure also has a second set of unit cells in the first conductive layer. The second set of unit cells are transposed relative to the first set of unit cells.

Abstract: A transistor gate structure includes a gate having gate sidewalls, a first side, and a second side opposite the first side. The first side may be coupled to a gate oxide layer, while the second side couples to an external device. The transistor structure also includes an inner gate spacer on the sidewalls of the gate, an outer gate spacer, and a middle gate spacer between the inner gate spacer and the outer gate spacer.

Abstract: A integrated circuit structure has a first test structure with a first set of un-landed vias. The first set of un-landed vias has a first side for each of the first set of un-landed vias proximate to a first BEOL layer (first back-end-of-line layer) of a chip and spaced apart, by a first gap, from the first BEOL layer. Each of the first set of un-landed vias has a first depth that is smaller than a landed depth of a chip via conductively connecting the first BEOL layer to a second BEOL layer of the chip. The first set of un-landed vias also has a second side for each of the first set of un-landed vias opposite the first side and connected to the second BEOL layer.

Abstract: Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail to distribute a first supply voltage to a Pwell region of corresponding SRAM bit cell rows. The SRAM strap cell also includes an N-type doped well (Nwell) tap electrically coupled to a second supply rail to distribute a second supply voltage to an Nwell region of corresponding SRAM bit cell rows. In one exemplary aspect, the Nwell tap can include multiple supply contacts used to couple the second supply rail to the SRAM strap cell to reduce mechanical stress in the Nwell tap. In another exemplary aspect, the Pwell tap can include non-active gates disposed across multiple Fins to stabilize the Fins and reduce or avoid mechanical stress in the Pwell tap.

Abstract: Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail to distribute a first supply voltage to a Pwell region of corresponding SRAM bit cell rows. The SRAM strap cell also includes an N-type doped well (Nwell) tap electrically coupled to a second supply rail to distribute a second supply voltage to an Nwell region of corresponding SRAM bit cell rows. In one exemplary aspect, the Nwell tap can include multiple supply contacts used to couple the second supply rail to the SRAM strap cell to reduce mechanical stress in the Nwell tap. In another exemplary aspect, the Pwell tap can include non-active gates disposed across multiple Fins to stabilize the Fins and reduce or avoid mechanical stress in the Pwell tap.

Abstract: A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.

Abstract: A multigate transistor device such as a fin-shaped field effect transistor (FinFET) is fabricated by applying a self-aligned diffusion break (SADB) mask having an opening positioned to expose an area of at least one portion of at least one gate stripe designated as at least one tie-off gate in the multigate transistor device and removing the tie-off gate through the opening of the SADB mask to isolate transistors adjacent to the tie-off gate.

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.

Abstract: A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.

Abstract: A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core.

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel.

Abstract: A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core.

Abstract: Complementary metal oxide semiconductor (CMOS) devices include input/output (I/O) devices and core function devices. A method includes forming first conduction type wells for the I/O devices and the core function devices with a well mask. Such a method also includes creating at least one baseline device of a first conduction type, at least one first threshold voltage device of the first conduction type, and at least one second threshold device of the first conduction type by tuning a conduction type drive current ratio with a threshold voltage mask. The method also includes controlling a gate critical dimension for the first conduction type devices and/or at least one second conduction type device using a gate mask.

Abstract: In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate.

Abstract: In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate.

Abstract: Techniques are provided for monitoring the performance of circuits and replacing low performing circuits with higher performing circuits. A frequency detector compares the frequency of a first periodic signal to the frequency of a second periodic signal. The difference in the frequency between the first periodic signal and the second periodic signal indirectly indicates how much the threshold voltages of the transistors have shifted. The difference in frequency between the two periodic signals can be monitored to determine the speed and performance of circuits on the chip. The output of the frequency detector can also indicate when to replace low performing circuits with higher performing circuits. When the frequency of the second periodic signal differs from the frequency of the first periodic signal by a predefined percentage, a low performing circuit is replaced with a higher performing replica circuit.

Abstract: Integrated circuits are stabilized by monitoring changes that affect circuit operation and by compensating for those changes using power supply adjustments. Changes in operating temperature and threshold voltage changes may be measured. Differential measurements may be made in which threshold voltages measured in continuously-biased monitoring circuits are compared to threshold voltages measured in intermittently-biased monitoring circuits. Temperature changes may be monitored using a temperature monitoring circuit based on an adjustable current source and a diode. Monitoring and compensation circuitry on the integrated circuits may use analog-to-digital and digital-to-analog converters controlled by a control unit to make temperature and threshold voltage measurements and corresponding compensating changes in power supply voltages.