Abstract: A nano-vacuum tube (NVT) transistor comprising a source having a knife edge, a drain, and a channel formed between the source and the drain, the channel having a width to provide a pseudo-vacuum in a normal atmosphere. The NVT transistor utilizing a space charge plasma formed at the knife edge within the channel.

Abstract: A nano-vacuum tube (NVT) transistor comprising a source having a knife edge, a drain, and a channel formed between the source and the drain, the channel having a width to provide a pseudo-vacuum in a normal atmosphere. The NVT transistor utilizing a space charge plasma formed at the knife edge within the channel.

Abstract: A nano-vacuum tube (NVT) transistor comprising a source having a knife edge, a drain, and a channel formed between the source and the drain, the channel having a width to provide a pseudo-vacuum in a normal atmosphere. The NVT transistor utilizing a space charge plasma formed at the knife edge within the channel.

Abstract: A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system while reducing contact degradation due to stress that results from differences in the coefficients of thermal expansion of the various components during thermal cycling

Abstract: A plurality of integrated circuits are efficiently interconnected to improve the electrical performance of the overall system. This is accomplished by providing high speed, high density, system level interconnect, including interchip routing lines, on the integrated circuit devices, thereby reducing the routing complexity of the substrate or board. The devices are mounted directly on the board. An integrated circuit device comprises an integrated circuit region including integrated circuit elements. An interconnect layer includes an insulative material, a plurality of conductive traces, and a plurality of conductive bond pads arranged in first and second subsets. A first subgroup of the conductive traces are connected to the integrated circuit elements in the integrated circuit region and are connected to the first subset of conductive bond pads.

Abstract: A method and a system for wafer level burn-in testing of a circuit featuring a flip-jumper to permit selectively connecting signals to the interconnect sites on the wafer that are in constant electrical communication with the circuit.

Abstract: Provided is a mount for an integrated circuit that features a routing carrier having first and second power planes and first and second signal layers. The first and second signal layers are disposed between the first and second power planes so that the return path for current propagating along the signal layers is in one of the adjacent power planes. To that end, another embodiment of the present invention provides that the distances between the signal layers and power planes are substantially constant over the volume of the routing carrier to ensure, which provides a constant impedance between one of the first and second signal layers and the power plane adjacent thereto.

Abstract: A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system while reducing contact degradation due to stress that results from differences in the coefficients of thermal expansion of the various components during thermal cycling.

Abstract: A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system. In one embodiment of the system of the present invention, a plurality of carriers corresponds to a plurality of ICs, and a board has a plurality of board regions for receiving the plurality of ICs and are arranged so as to be attached to a backplane forming a vertical stack of boards.

Abstract: A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system. In one embodiment of the system of the present invention, a plurality of carriers corresponds to a plurality of ICs, and a board has a plurality of board regions for receiving the plurality of ICs. In one embodiment of the method of the present invention, a carrier is provided for each IC in a complex IC. A board having openings is provided, and the ICs are fitted into the board openings with the carriers mounted thereto.

Abstract: An electronic digital dual processor system including an interface to an external memory in addition to an internal memory. The dual processor architecture includes dual independent and simultaneously operable registers for the temporary storage of data from an arithmetic and logic unit and for memory addressing. The internal memory includes a ROM for storing instructions and a RAM for storing data. The internal memory is also used to store instructions. Control and timing circuitry is included for the generation of microinstructions for the instructions stored in the memory. The control and timing circuitry provide for the simultaneous and independent execution of the microinstructions involving the dual register sets.

Abstract: A two player game apparatus includes the inputs for the first and second player, together with display for each player with a common display for providing the game status connected to a single electronic digital processor. The processor system further includes two central processing units where one central processing unit performs the game algorithm for one player and the second central processing unit performs the game algorithm for the second player. Each individual's central processing unit provides individual player status for its player input. Both central processing units provide data for the common display.

Abstract: An electronic digital processing system implemented on a single MOS/LSI semiconductor chip including a ROM for storing instruction codes, a RAM for storing data, an arithmetic logic unit for performing operations on data under control of microinstructions or commands, control circuitry for generating commands in response to the instruction codes in a plurality of central processing units. The fetching of instructions from the ROM, the accessing of data from the RAM, the operation of the arithmetic unit are controlled by the central processing units which share the same data paths that couple the central processing units to the ROM, RAM, arithmetic unit and control circuitry.

Abstract: An electronic apparatus with processing capability dedicated to the display function. This apparatus includes a keyboard for inputting data into the processor system and a display for presentation of the output data from the processor system. The electronic digital processor system includes a memory, an arithmetic and logic unit and two central processing units that operate independently and simultaneously. The keyboard input is connected to one central processing unit and the display is connected to the second central processing unit. The algorithm in the first central processing unit is dedicated to obtaining inputs from the keyboard and performing certain operations defined by the function of the apparatus. The algorithm contained in the second central processing unit is dedicated to the display of output data contained in a RAM in the digital processor system. Since both central processing units operate simultaneously and independently, they both use the same locations in RAM.

Abstract: An electronic digital processor system including a plurality of processing units with dedicated input port and output port for each of the processing units and an output port that is shared by the processing units. The digital processor system also includes a ROM for the storage of commands, a RAM for the storage of data, an arithmetic and logic unit for performing operations on the data, two independent and simultaneously operable processing units for executing these commands on the data and the control circuit for providing for simultaneous execution of commands in both processing units.

Abstract: An electronic telephone including a keyboard input, a telephone line interface, a speech synthesis device with a control line and an audio line coupled to the telephone line interface, a message recorder with an audio line coupled to a telephone line interface, and an electronic digital processor system to control the device. The electronic digital processor system includes two independent and separably operable central processing units. One central processing unit is activated by the keyboard when a telephone number is input and may be used to store numerous, frequently called telephone numbers.