Abstract: An SCR switch of a switch mode power supply is coupled between an unregulated supply voltage and a filter capacitor. A regulator oscillator generates trigger pulses for controlling a switching operation of the SCR switch of the power supply to produce an output supply voltage that energizes a deflection circuit. The regulator oscillator produces trigger pulses that are applied to the SCR switch during both power-up and power-off operation. A resistor coupled between the unregulated supply voltage and the filter capacitor maintains the filter capacitor charged during power-off operation to prevent the trigger pulses from causing the latching operation in the SCR switch throughout the power-off operation. In this way, an audible parasitic vibration sound is not being generated by the power supply during the power-off operation.

Abstract: A phase-lock loop circuit of a television apparatus is synchronized by a horizontal synchronizing input signal. The phase-lock loop circuit includes a frequency-to-voltage converter that is responsive, during vertical trace, to the synchronizing input signal for generating a control voltage indicative of the frequency of the synchronizing input signal. During vertical trace, the control voltage varies the free running frequency of a controlled oscillator of the phase-lock loop circuit such that the free running frequency of the oscillator is directly related to the frequency of the input signal. During vertical retrace, the frequency-to-voltage converter is responsive to the oscillator output signal for generating the control signal that maintains the free running frequency of the oscillator substantially unchanged during vertical retrace.

Abstract: A refresh circuit for a dynamic semiconductor memory wherein each access to the main semiconductor memory for the storage or retrieval of information is detected and recorded in an auxiliary memory. During each memory access, the memory row being accessed is automatically refreshed as part of the storage or retrieval process. In accordance with the invention, the auxiliary memory is examined prior to the commencement of a refresh cycle and if a particular row in the main memory has been accessed during the current refresh cycle, that row is not refreshed but is skipped until the next refresh cycle, at which time the need for a refresh signal is again determined.

Abstract: Multiple usage requests for a common resource, such as a memory system, are given usage priorities by a multiple request arbitration circuit. Priority is given to a predetermined one of the input signals occurring prior to any one of the remaining input signals and priority is also given to the one input signal if it occurs within a predetermined interval subsequent to any one of the remaining input signals. The circuit also provides for the suppression of voltage transients which may occur upon the essentially simultaneous occurrence of more than one input signal and the circuit also provides a faster access time for input signals other than the predetermined one of the input signals.