Abstract: A simple, low-cost circuit and method for line zing parasitic capacitances of transistor junctions, independent of the process technology employed, are provided. In the preferred embodiment, the parasitic capacitance of a transistor in a track and hold circuit is linearized by providing a pair of diodes that act inversely to the parasitic diodes formed within the integrated circuit during normal tracking operations. Without the diodes of the present invention, the varying input signals cause the parasitic capacitance to vary, thereby causing harmonic distortion in the track and hold circuit. An alternate embodiment of the present invention is also provided in which a second complementary transistor is provided. The inclusion of the complementary transistor results in a second set of parasitic capacitances that are substantially opposite the parasitic capacitances of the track and hold transistor.

Abstract: Power shutdown of an integrated circuit such as a data acquisition system is implemented by software command. In one embodiment of a data acquisition system, an 8 bit data input word for configuring the operation of the data acquisition system includes two word length bits which define the length of data output words. One combination of the word length bits is utilized to command power shutdown. A decoder within the integrated circuit identifies the power shutdown command and generates a power shutdown signal (PS) to minimize power consumption when the circuit is not in operation.

Abstract: A general purpose active filter which can be fabricated as a single, monolithic IC. The IC includes two independent filter building blocks. Each filter block includes a pair of serially connected summers and a pair of serially connected switched capacitor positive integrators connected to the serial output of the summers. The IC further includes clock interface circuitry for receiving and conditioning first and second external clock signals. The interface circuitry drives the switches of the positive integrators of each filter block with one of the first and second conditioned clock signals. A plurality of input and output leads are interconnected with the components of each filter block to permit the filter blocks to be separately configured to perform various second order filter functions. The filter blocks may be tuned according to external resistance ratios and/or according to the frequencies of the external clock signals.