Abstract: The present invention provides a programmable pin that may be selectively configured to operate as a signal pin or a power pin. A programmable pin provides increased flexibility in the design of integrated circuit devices. Programmable pins may also be used to provide better performance of the entire integrated circuit device and reduce noise in the pins of the integrated circuit device that are signal pins. The programmable pin may also include the function of retaining the last asserted state on the pin. Memory provides further functionality and flexibility in the design of integrated circuit devices.

Abstract: A memory circuit with a low power programming voltage switch for reduced leakage current during a read operation. The apparatus includes a high voltage switch which, in a programming mode receives a high (e.g. programming) voltage and in another mode (reading) receives a normal range voltage, and a line driver which drivers a selection or non-selection voltage into word lines or column select lines into a memory array. During a read mode, the deselected line drivers and high voltage switches are operated in a reduced leakage current mode such that leakage current is forced through selected line drivers and their high voltage switches before being forced through the deselected line drivers such that the leakage current is limited to the number of selected line drivers.

Abstract: A variable slew control for output circuits is disclosed. The slew control circuit automatically adjusts the rate in which voltage on a slew node is driven to a reference voltage, minimizing noise at the output device driver. The variable slew control decreases the slew rate of the slew node during periods when di/dt is at a high level, but allows the voltage on the slew node to drop at faster rates during times when di/dt at the output driver is low.