Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects, for example. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

Abstract: In a memory subsystem, a physical interface (PHY) has an unmatched architecture. To compensate for the unmatched architecture, the PHY has variable delay compensation to adjust for propagation mismatch of analog signals in the data (DQ) path and data strobe (DQS) path of the PHY. The variable delay compensation can be provided by adjusting the operation of a digital component of the PHY to introduce the delay compensation.

Abstract: Techniques and mechanisms for managing a delivery of power to a resource of an input/output (I/O) interface. In an embodiment, a first link of a plurality of communication links is monitored. Of the plurality of links, a first set of resources of the I/O interface is to support communication only via the first link. One or more other resources of the I/O interface are for supporting communications of another link of the plurality of links. In another embodiment, a resource of the first set of resources is decoupled from a power supply in response to detecting a total number of active lanes of the first link, decoupling.

Abstract: Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions. Embodiments of the invention may comprise of logic, modules or any combination thereof, to detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards its respective memory unit(s), a processor core executing a processor low-power mode, and a processor socket (operatively coupling the processing core and the memory unit) executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit(s) and various components of the memory subsystem.

Abstract: Techniques and mechanisms for managing a delivery of power to a resource of an input/output (I/O) interface. In an embodiment, a first link of a plurality of communication links is monitored. Of the plurality of links, a first set of resources of the I/O interface is to support communication only via the first link. One or more other resources of the I/O interface are for supporting communications of another link of the plurality of links. In another embodiment, a resource of the first set of resources is decoupled from a power supply in response to detecting a total number of active lanes of the first link, decoupling.

Abstract: Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions. Embodiments of the invention may comprise of logic, modules or any combination thereof, to detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards its respective memory unit(s), a processor core executing a processor low-power mode, and a processor socket (operatively coupling the processing core and the memory unit) executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit(s) and various components of the memory subsystem.