Patents by Inventor Sampath Ratnam

Sampath Ratnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446197
    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley
  • Patent number: 10430116
    Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Singidi, Sampath Ratnam, Renato C. Padilla, Jr., Gary F. Besinga, Peter Sean Feeley
  • Publication number: 20190295660
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Publication number: 20190278653
    Abstract: A system configured to determine that a trigger condition has occurred that is related to an operation performed on a memory device of the system. Responsive to determining that the trigger condition has occurred, reordering error handling mechanisms of an error handling sequence based upon an error handling mechanism performance metric. Each error handling mechanism specifies operations to be performed to recover an error in the operation on the memory device.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 12, 2019
    Inventors: Renato Padilla, JR., Gary F. Besinga, Harish Singidi, Gianni Stephen Alsasua, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam
  • Patent number: 10366763
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harish Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Michael G. Miller
  • Patent number: 10365854
    Abstract: A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Ashutosh Malshe, Sampath Ratnam, Harish Singidi, Vamsi Pavan Rayaprolu
  • Patent number: 10354732
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Thomson, Harish Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • Patent number: 10347344
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Patent number: 10283205
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 7, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Harish Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, John Zhang, Jie Zhou
  • Publication number: 20190130980
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Inventors: Harish Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Michael G. Miler
  • Publication number: 20190122705
    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Reddy Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley
  • Publication number: 20190103164
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Application
    Filed: September 30, 2017
    Publication date: April 4, 2019
    Inventors: Ashutosh Malshe, Harish Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, John Zhang, Jie Zhou
  • Publication number: 20190065108
    Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Singidi, Sampath Ratnam, Renan Padilla, Gary F. Besinga, Peter Sean Feeley
  • Publication number: 20190066739
    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley
  • Publication number: 20190066792
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Thomson, Harish Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • Publication number: 20190066802
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Inventors: Ashutosh Malshe, Kishore Kumar Muchhert, Harish Singidi, Peter Sean Feeley, Sampath Ratnam, kulachet Tanpairoj, Ting Luo
  • Patent number: 9183070
    Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Todd Marquart, Sampath Ratnam, Sean Eilert
  • Publication number: 20150033087
    Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.
    Type: Application
    Filed: July 24, 2013
    Publication date: January 29, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Todd Marquart, Sampath Ratnam, Sean Eilert