Patents by Inventor Sampath Ratnam

Sampath Ratnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110669
    Abstract: The disclosure configures a memory sub-system controller to store random data in a different layout from sequential data. The controller receives a request to store a set of data to a set of memory components. The controller determines whether the set of data corresponds to either sequential data or random data and selects a write cursor from a plurality of write cursors to associate with the set of data in response to determining whether the set of data corresponds to the sequential data or the random data. The controller programs the set of data to one or more of the set of memory components according to a data layout associated with the selected write cursor.
    Type: Application
    Filed: July 30, 2024
    Publication date: April 3, 2025
    Inventors: Sundararajan Sankaranarayanan, Sampath Ratnam, Jiangang Wu, Chandra Mouli Guda, Steven R. Brown, Ashutosh Malshe
  • Publication number: 20250053329
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to receive information from a host about invalidated memory addresses. The controller receives, from a host, data identifying a set of storage locations associated with invalidated data stored in a set of memory components and, in response to receiving the data, performs staging activity for the invalidated data stored in the set of storage locations. The controller receives, from the host, a trim command for one or more storage locations in the set of storage locations and performs trim operations for the one or more storage locations for which the staging activity has already been performed.
    Type: Application
    Filed: July 29, 2024
    Publication date: February 13, 2025
    Inventors: Sampath Ratnam, Daniel J. Hubbard, Kevin R. Brandt, David Ebsen, Brent Carl Byron
  • Publication number: 20250036303
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to control storage on the memory sub-system based on endurance of memory components. The controller groups the set of memory components into a plurality of categories representing different endurance levels of the set of memory components and communicates, to a host, information about the plurality of categories. The controller receives, from the host, a request to program data into an individual memory component of the set of memory components, the request being generated by the host based on a type of the data and an individual category associated with the individual memory component.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 30, 2025
    Inventors: Kevin R. Brandt, Sampath Ratnam, David Ebsen, Brent Carl Byron, Daniel J. Hubbard
  • Publication number: 20250028600
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to configure data storage policies on the memory sub-system. The controller receives, from a host, a data storage policy instruction, the data storage policy instruction defining how data is stored on a set of memory components. The controller updates configuration information for the memory sub-system based on the data storage policy instruction received from the host and controls storage of data to the set of memory components based on the updated configuration information.
    Type: Application
    Filed: July 19, 2024
    Publication date: January 23, 2025
    Inventors: Brent Carl Byron, Kevin R. Brandt, Sampath Ratnam, David Ebsen, Daniel J. Hubbard
  • Publication number: 20250028483
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to deallocate data prior to folding operations. The controller generates an instruction to fold data stored in an individual portion of the set of memory components. The controller, prior to executing the instruction to fold the data stored in the individual portion of the set of memory components, transmits a communication to a host indicative of the instruction to fold the data stored in the individual portion. The controller conditions execution of the instruction to fold the data stored in the individual portion of the set of memory components based on transmission of the communication to the host.
    Type: Application
    Filed: July 17, 2024
    Publication date: January 23, 2025
    Inventors: Daniel J. Hubbard, Kevin R. Brandt, David Ebsen, Sampath Ratnam, Brent Carl Byron
  • Publication number: 20250028479
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to inform a host about write amplification penalty for host invalidations. The controller generates a virtual memory group comprising a portion of a memory component of a set of memory components. The controller computes a write amplification penalty associated with invalidating data associated with the virtual memory group. The controller communicates, to a host, information about the write amplification penalty associated with invalidating data associated with the virtual memory group. The controller receives, from the host, a request to invalidate data associated with the virtual memory group, the request being generated by the host based on the write amplification penalty.
    Type: Application
    Filed: July 18, 2024
    Publication date: January 23, 2025
    Inventors: David Ebsen, Daniel J. Hubbard, Kevin R. Brandt, Sampath Ratnam, Brent Carl Byron
  • Publication number: 20250021253
    Abstract: Various embodiments provide for processing write requests on a memory system based on queue identifiers associated with the write requests. In particular, input data streams can be received and stored by submission queues of a memory system, and write requests in the input data streams can be separated and processed based on queue identifiers associated with the submission queues using an inline approach for writing data on the memory system, an offline approach for writing data on the memory system, or both.
    Type: Application
    Filed: July 12, 2024
    Publication date: January 16, 2025
    Inventors: Luca Bert, Sampath Ratnam
  • Publication number: 20250021269
    Abstract: Various embodiments provide for performing a preconditioned operation on a memory system (e.g., the memory sub-system) based on queue identifiers of command requests received from a host system, where the precondition can include detection of command requests to be performed (e.g., executed) with respect to a sequence of memory addresses.
    Type: Application
    Filed: July 12, 2024
    Publication date: January 16, 2025
    Inventors: Luca Bert, Sampath Ratnam
  • Publication number: 20250021267
    Abstract: Various embodiments provide for block caching with queue identifiers on a memory system. In particular, when a write request to write host data is executed on a memory system that uses write/block caching and the host data is written to one or more cache blocks of a memory device of the memory system, the memory system can cause the queue identifier of the write request to be stored on the memory system in association with the host data. Subsequently, when the memory system moves (e.g., de-stages) data from one or more cache blocks (e.g., single-level cell (SLC) blocks) to one or more non-cache blocks (e.g., quad-level cell (QLC) blocks), the memory system can do so based on queue identifiers associated with host data written on one or more cache blocks of the memory system.
    Type: Application
    Filed: July 12, 2024
    Publication date: January 16, 2025
    Inventors: Luca Bert, Sampath Ratnam
  • Publication number: 20250021268
    Abstract: Various embodiments provide for performing one or more data read-ahead operations on a memory system based on a read size and a queue identifier of a read request. In particular, a memory system of some embodiments is configured to perform at least one read-ahead operation when an individual read request, received from a host system in association with a queue identifier, has a read size equal to a maximum data transfer size (MDTS) of the memory system.
    Type: Application
    Filed: July 12, 2024
    Publication date: January 16, 2025
    Inventors: Luca Bert, Sampath Ratnam
  • Publication number: 20240282390
    Abstract: Various embodiments use a feedback-control loop to track slow charge loss (SCL) for a memory cell of a memory device, which can be used to adjust one or more read level voltages used to read data from the memory cell.
    Type: Application
    Filed: February 21, 2024
    Publication date: August 22, 2024
    Inventors: Lei Zhang, Sampath Ratnam, Steven Michael Kientz
  • Publication number: 20240231676
    Abstract: An amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell
  • Publication number: 20240176698
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Patrick Khayat, Sampath Ratnam, Kishore Kumar Muchherla, Jiangang Wu, James Fitzpatrick
  • Patent number: 11966616
    Abstract: A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell
  • Patent number: 11934266
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Patrick Khayat, Sampath Ratnam, Kishore Kumar Muchherla, Jiangang Wu, James Fitzpatrick
  • Publication number: 20240069788
    Abstract: In some implementations, a controller of a memory device may obtain a first metric associated with a memory of the memory device using a first memory read configuration. The controller may apply a function to the first metric to obtain a second memory read configuration. The controller may obtain a second metric associated with the memory using the second memory read configuration. The controller may filter the first metric and the second metric to obtain a first filtered metric and a second filtered metric. The controller may provide the first filtered metric and the second filtered metric to a memory management process executing on the controller. The controller may perform an action based on an output of the memory management process, wherein the output is based on the first filtered metric and the second filtered metric.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Dung Viet NGUYEN, Shantilal Rayshi DORU, Jun WAN, Sampath RATNAM
  • Patent number: 11887651
    Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Renato Padilla, Jr.
  • Publication number: 20230393938
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.
    Type: Application
    Filed: July 7, 2022
    Publication date: December 7, 2023
    Inventors: Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Patrick Khayat, Sampath Ratnam, Kishore Kumar Muchherla, Jiangang Wu, James Fitzpatrick
  • Patent number: 11823748
    Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Karl Schuh, Mustafa N Kaynak, Xiangang Luo, Shane Nowell, Devin Batutis, Sivagnanam Parthasarathy, Sampath Ratnam, Jiangang Wu, Peter Feeley
  • Patent number: 11709633
    Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Peter Sean Feeley, Ashutosh Malshe, Renato Padilla, Jr., Kishore Kumar Muchherla, Sampath Ratnam