Patents by Inventor Sampath Ratnam

Sampath Ratnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10915395
    Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ting Luo, Kishore Kumar Muchherla, Harish Reddy Singidi, Xiangang Luo, Renato Padilla, Jr., Gary F. Besinga, Sampath Ratnam, Vamsi Pavan Rayaprolu
  • Publication number: 20210027846
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 28, 2021
    Inventors: Ashutosh Malshe, Harish Reddy Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, Xu Zhang, Jie Zhou
  • Publication number: 20200411083
    Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Retano Padilla, JR.
  • Publication number: 20200411117
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Patent number: 10818361
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Harish Reddy Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, Xu Zhang, Jie Zhou
  • Publication number: 20200335172
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Micheal G. Miller
  • Publication number: 20200319827
    Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, JR.
  • Patent number: 10796745
    Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Renato Padilla, Jr.
  • Patent number: 10777284
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Publication number: 20200278814
    Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Peter Sean Feeley, Ashutosh Malshe, Renato Padilla, JR., Kishore Kumar Muchherla, Sampath Ratnam
  • Patent number: 10755792
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Michael G. Miller
  • Publication number: 20200258578
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 13, 2020
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • Publication number: 20200251162
    Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Renato Padilla, JR.
  • Publication number: 20200234775
    Abstract: A memory sub-system can be determined to be operating within a target operating characteristic based on a threshold success rate associated with error control operations using a particular parameter. Upon determining that the memory sub-system is operating within the target operating characteristic, a sticky read mode is entered by performing subsequent read operations using the particular parameter. It is determined that additional error control operations are triggered for at least a first threshold number of read operations using the particular parameter during the sticky read mode. Upon determining that the additional error control operations are triggered for at least the first threshold number of read operations using the particular parameter during the sticky read mode, the sticky read mode is exited by performing further read operations using a default parameter associated with the memory sub-system.
    Type: Application
    Filed: April 9, 2020
    Publication date: July 23, 2020
    Inventors: Harish Singidi, Kishore Muchherla, Ashutosh Malshe, Vamsi Rayaprolu, Sampath Ratnam, Renato Padilla, JR., Michael Miller
  • Patent number: 10719271
    Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, Jr.
  • Patent number: 10691377
    Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Peter Sean Feeley, Ashutosh Malshe, Renato Padilla, Jr., Kishore Kumar Muchherla, Sampath Ratnam
  • Patent number: 10679704
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • Publication number: 20200176063
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Patent number: 10672452
    Abstract: Devices and techniques for temperature informed memory refresh are described herein. Temperature data can be updated in response to a memory component write performed under an extreme temperature. Here, the write is performed on a memory component element in the memory component. The memory component element can be sorted above other memory component elements in the memory component based on the temperature data. Once sorted to the top of these memory component elements, a refresh can be performed the memory component element.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Renato Padilla, Jr.
  • Publication number: 20200159446
    Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, JR.