Patents by Inventor Sampei Miyamoto
Sampei Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080284504Abstract: This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET.Type: ApplicationFiled: June 17, 2008Publication date: November 20, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventors: Makoto Hirota, Hidekazu Kikuchi, Sampei Miyamoto
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Publication number: 20070121358Abstract: This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET.Type: ApplicationFiled: November 7, 2006Publication date: May 31, 2007Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventors: Makoto HIROTA, Hidekazu KIKUCHI, Sampei MIYAMOTO
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Patent number: 6134153Abstract: A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle.Type: GrantFiled: July 29, 1999Date of Patent: October 17, 2000Assignees: Mosaid Technologies Incorporated, Oki Electric Industry Co. Ltd.Inventors: Valerie Lines, Cynthia Mar, Xiao Luo, Sampei Miyamoto
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Patent number: 5982674Abstract: A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle.Type: GrantFiled: September 30, 1998Date of Patent: November 9, 1999Assignees: Mosaid Technologies Incorporated, Oki Electric Industry Co. Ltd.Inventors: Valeria Lines, Cynthia Mar, Xiao Luo, Sampei Miyamoto
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Patent number: 5850362Abstract: A memory device according to the invention has a first pair of bit lines, having first and second bit lines, coupled to a first memory cell which cause a first potential difference between the first and second bit lines; a second pair of bit lines, having third and fourth bit lines, coupled to a second memory cell which causes a second potential difference between the third and fourth bit lines; a first sense amplifier having first and second transistors each of which is a first conductivity type, the gate electrode of said first transistor being connected to said first bit line, the first electrode of the first transistor being connected to the second bit line, the gate electrode of the second transistor being connected to the second bit line, the first electrode of the second transistor being connected to the first bit line; a second sense amplifier having third and fourth transistors each of which is the first conductivity type, the gate electrode of the third transistor being connected to the third bit liType: GrantFiled: March 21, 1996Date of Patent: December 15, 1998Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinzo Sakuma, Sampei Miyamoto
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Patent number: 5818787Abstract: A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.Type: GrantFiled: April 3, 1997Date of Patent: October 6, 1998Assignee: Oki Electric Industry Co., Ltd.Inventors: Sampei Miyamoto, Tamihiro Ishimura
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Patent number: 5699316Abstract: A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.Type: GrantFiled: October 12, 1995Date of Patent: December 16, 1997Assignee: Oki Electric Industry Co., Ltd.Inventors: Katsuaki Matsui, Tamihiro Ishimura, Sampei Miyamoto
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Patent number: 5686752Abstract: A PMOS 21 and an NMOS 22, which are connected in series between a power supply potential Vcc and a ground potential Vss, perform ON and Off operation in accordance with data signals G1 and G2 from an output buffer control circuit 40, and generate an output signal. A Vpp generating circuit 50 generates a potential Vpp higher than the power supply potential Vcc and a back gate bias of the PMOS 21 is set at the potential Vpp. Even if a latch-up trigger current due to a surge voltage is produced, the back gate bias of the PMOS 21 is set at Vpp and therefore a potential difference caused in an N type well resistor becomes small and a base potential of a parasitic bipolar transistor disposed between the N type well 2 and a substrate 1 becomes approximate to the potential Vpp. Accordingly, the current which flows into the substrate 1 is suppressed and a latch-up tolerance is improved.Type: GrantFiled: December 21, 1995Date of Patent: November 11, 1997Assignee: Oki Electric Industry Co., Ltd.Inventors: Tamihiro Ishimura, Sampei Miyamoto
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Patent number: 5625315Abstract: A booster power generating circuit according to the present invention comprises first to fourth booster circuits for supplying first to fourth booster potentials to first to fourth nodes in response to first to fourth pulse signals, a first precharge circuit for precharging the first node when controlled by the fourth booster potential from the fourth node, a second precharge circuit for precharging the third node when controlled by the second booster potential from the second node and a first output circuit for outputting the first booster potential of the first node to an output node, whereby a given booster potential can be output since there is no voltage drop of the boosted potential of the second and fourth nodes, there is obtained high potential between the first and third precharge circuits and the precharging speed of the first and third node is not slowed.Type: GrantFiled: September 18, 1995Date of Patent: April 29, 1997Assignee: Oki Electric Industry Co., Ltd.Inventors: Katsuaki Matsui, Sampei Miyamoto, Hidekazu Kikuchi
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Patent number: 5521869Abstract: A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.Type: GrantFiled: November 30, 1994Date of Patent: May 28, 1996Assignee: OKI Electric Industry Co., Ltd.Inventors: Tamihiro Ishimura, Sampei Miyamoto
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Patent number: 5502415Abstract: A booster power generating circuit according to the present invention comprises first to fourth booster circuits for supplying first to fourth booster potentials to first to fourth nodes in response to first to fourth pulse signals, a first precharge circuit for precharging the first node when controlled by the fourth booster potential from the fourth node, a second precharge circuit for precharging the third node when controlled by the second booster potential from the second node and a first output circuit for outputting the first booster potential of the first node to an output node, whereby a given booster potential can be output since there is no voltage drop of the boosted potential of the second and fourth nodes, there is obtained high potential between the first and third precharge circuits and the precharging speed of the first and third node is not slowed.Type: GrantFiled: June 29, 1994Date of Patent: March 26, 1996Assignee: Oki Electric Industry Co., Ltd.Inventors: Katsuaki Matsui, Sampei Miyamoto, Hidekazu Kikuchi
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Patent number: 5452260Abstract: A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First, to third memory cell blocks respectively have memory cell groups each including memory cells. First, to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal.Type: GrantFiled: March 21, 1994Date of Patent: September 19, 1995Assignee: Oki Electric Industry Co., Ltd.Inventors: Katsuaki Matsui, Sampei Miyamoto, Tamihiro Ishimura
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Patent number: 5422853Abstract: A sense amplifier control circuit supplies a first potential to the sense amplifiers of a semiconductor memory through a set of first control transistors, each coupled in parallel to at least two and at most four sense-amplifier nodes. The first transistors are switched by a first control signal line. A second potential may be supplied to the sense amplifiers through a similar set of second control transistors, which are switched by a second control signal line. The first and second control signal lines may be driven independently, or one or both control signal lines may be driven by a set of drivers coupled in parallel between the two control signal lines.Type: GrantFiled: November 23, 1993Date of Patent: June 6, 1995Assignee: Oki Electric Industry Co., Ltd.Inventor: Sampei Miyamoto
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Patent number: 5394374Abstract: A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.Type: GrantFiled: March 3, 1993Date of Patent: February 28, 1995Assignee: Oki Electric Industry Co., Ltd.Inventors: Tamihiro Ishimura, Sampei Miyamoto
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Patent number: 5394368Abstract: A semiconductor memory device having a redundancy circuit having a large flexibility, wherein a plurality of fuse columns are operated by address signals.Type: GrantFiled: June 21, 1993Date of Patent: February 28, 1995Assignee: Oki Electric Industry Co., Ltd.Inventor: Sampei Miyamoto
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Patent number: 5363331Abstract: A semiconductor memory device has plural memory cell blocks, each including memory cells storing data therein. A data bus and switching circuits transfer data from the memory cells to the data bus in response to a first logic level signal applied thereto. Column lines each have first and second ends. Each column line is connected to the corresponding switching circuit in each of the memory cell blocks. A column decoder, coupled to the first end of the column lines, provides the first logic level signal to one of the column lines upon the memory cell blocks being accessed. Potential setting circuits are coupled to the second end of the column lines, and preliminarily set the respective column lines to be in a predetermined potential so that each switching circuit is inactive prior to the column decoder providing the first logic level signal. All the memory cells in an array can be prevented from becoming inoperative even if a column line is broken.Type: GrantFiled: December 22, 1992Date of Patent: November 8, 1994Assignee: Oki Electric Industry Co., Ltd.Inventors: Katsuaki Matsui, Sampei Miyamoto
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Patent number: 5313426Abstract: A memory device according to the invention has a first pair of bit lines, having first and second bit lines, being coupled to a first memory cell which cause a first potential difference between the first and second bit lines; a second pair of bit lines, having third and fourth bit lines, coupled to a second memory cell which causes a second potential difference between the third and fourth bit lines; a first sense amplifier having first and second transistors each of which is a first conductivity type, the gate electrode of said first transistor being connected to said first bit line, the first electrode of the first transistor being connected to the second bit line, the gate electrode of the second transistor being connected to the second bit line, the first electrode of the second transistor being connected to the first bit line; a second sense amplifier having third and fourth transistors each of which is the first conductivity type, the gate electrode of the third transistor being connected to the thirdType: GrantFiled: December 7, 1992Date of Patent: May 17, 1994Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinzo Sakuma, Sampei Miyamoto
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Patent number: 5297105Abstract: A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First to third memory cell blocks respectively have memory cell groups each including memory cells. First to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal.Type: GrantFiled: March 12, 1993Date of Patent: March 22, 1994Assignee: Oki Electric Industry Co., Ltd.Inventors: Katsuaki Matsui, Sampei Miyamoto, Tamihiro Ishimura
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Patent number: 5113088Abstract: Substrate bias generating circuitry for generating a substrate bias to be applied to the substrate of an integrated circuit. The circuitry includes an oscillator circuit for generating oscillator pulses having a predetermined frequency. A charge pump circuit has a capacitor and charges and discharges the capacitor in response to the oscillator pulses for generating the substrate bias. A substrate bias level sensing circuit is responsive to the voltage level of the substrate bias for outputting a control signal associated with the sensed voltage level. The level sensing circuit has a level holding subcircuit for holding the control signal in an enabled state at least for a predetermined duration which is four times as long as a period of time necessary for the charge pump circuit to complete a pumping operation. The pumping operation of the charge pump circuit is controlled by the control signal.Type: GrantFiled: May 7, 1990Date of Patent: May 12, 1992Assignee: Oki Electric Industry Co., Ltd.Inventors: Takayuki Yamamoto, Sampei Miyamoto
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Patent number: 4843258Abstract: A drive circuit for driving a semiconductor device includes a reference voltage level generator for outputting a reference voltage level which is associated with an input voltage level from an external power source. Supplied with the reference level, a ring oscillator oscillates a frequency signal having a predetermined frequency. A drive voltage level generator responds to the reference level and the frequency signal for producing a drive voltage level which is constantly substantially equal to the reference level in synchronism with the frequency signal. The drive voltage level generator feeds power from the external power source to the semiconductor device at the drive level, thereby driving the semiconductor load circuit.Type: GrantFiled: July 29, 1988Date of Patent: June 27, 1989Assignee: Oki Electric Industry Co., Ltd.Inventors: Masahumi Miyawaki, Sampei Miyamoto, Tamihiro Ishimura