Patents by Inventor Samphy Hong

Samphy Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145217
    Abstract: Methods for processing a dielectric film to improve its uniformity of thickness and refractive index are disclosed. The dielectric film is deposited using conventional approaches, such as chemical vapor deposition (CVD) or spin coating. The workpiece, with the applied dielectric film is then processed to improve the uniformity of the thickness. This processing may comprise implanting a thinning species to the thicker portions of the dielectric film to reduce the thickness of these portions. The thinning species may be silicon or another suitable species. This processing may alternatively or additionally include implanting a thickening species to the thinner portions of the dielectric film to increase their thickness. The thickening species may be helium or another suitable species. This approach may reduce the variation in thickness by 50% or more.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Qintao Zhang, Eric Jay Simmons, JR., Jared Traynor, Wei Zou, Miguel Fung, Samphy Hong
  • Publication number: 20240128131
    Abstract: A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Avishay Vaxman, Qintao Zhang, Jeffrey P. Koch, David P. Surdock, Wayne R. Swart, David J. Lee, Samphy Hong, Aldrin Bernard Vincent Eddy, Daniel G. Deyo
  • Patent number: 11804537
    Abstract: Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: October 31, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Wei Zou, Hans-Joachim L. Gossmann
  • Patent number: 11798982
    Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: October 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Jason Appell, David J. Lee
  • Patent number: 11721743
    Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Wei Zou, Samphy Hong
  • Patent number: 11695060
    Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: July 4, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Wei Zou, Lei Zhong, David J. Lee, Felix Levitov
  • Publication number: 20230178373
    Abstract: Disclosed herein are methods for increasing MOSFET threshold voltage to enable higher SiC mobility. In some embodiments, a method includes providing a device structure including a dielectric layer over an epitaxial layer, patterning a hardmask layer over the dielectric layer, performing a first ion implant to form a well in the epitaxial layer, and performing a second ion implant to form an interface layer between the well and the dielectric layer.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Wei Zou
  • Publication number: 20230040358
    Abstract: Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong
  • Publication number: 20220415656
    Abstract: Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Vittoriano Ruscio, Wei Zou, David J. Lee
  • Publication number: 20220415657
    Abstract: Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Wei Zou, Judy Campbell Soukup
  • Patent number: 11527412
    Abstract: A method for performing an ion implantation process including providing a hardmask layer disposed atop a substrate, providing a photoresist layer disposed atop the hardmask layer and defining a pattern exposing a portion of the hardmask layer, performing a room temperature ion implantation process wherein an ion beam formed of an ionized first dopant species is directed onto the exposed portion of the hardmask layer to make the exposed portion more susceptible to ion etching or wet etching, performing an etching process wherein the exposed portion of the hardmask layer is etched away to expose an underlying portion of the substrate, and performing a high energy, hot ion implantation process wherein an ion beam formed of a ionized second dopant species is directed onto the exposed portion of the substrate.
    Type: Grant
    Filed: December 6, 2020
    Date of Patent: December 13, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, David J. Lee, Felix Levitov, Lei Zhong, Wei Zou
  • Patent number: 11527637
    Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming an oxide layer over the device structure including within each of the plurality of trenches and over a top surface of the device structure, and implanting a first portion of the oxide layer using an ion implant delivered to the device structure at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the device structure. The method may further include removing the oxide layer from the top surface of the device structure and from a sidewall of each of the plurality of trenches, wherein a second portion of the oxide layer remains along a bottom of each of the plurality of trenches.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: December 13, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong
  • Publication number: 20220359710
    Abstract: Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.
    Type: Application
    Filed: May 4, 2021
    Publication date: November 10, 2022
    Inventors: Qintao Zhang, Samphy Hong, Wei Zou, Hans-Joachim L. Gossmann
  • Publication number: 20220344453
    Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Jason Appell, David J. Lee
  • Patent number: 11437488
    Abstract: Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: September 6, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, David J. Lee, Jason Appell
  • Publication number: 20220278221
    Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming an oxide layer over the device structure including within each of the plurality of trenches and over a top surface of the device structure, and implanting a first portion of the oxide layer using an ion implant delivered to the device structure at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the device structure. The method may further include removing the oxide layer from the top surface of the device structure and from a sidewall of each of the plurality of trenches, wherein a second portion of the oxide layer remains along a bottom of each of the plurality of trenches.
    Type: Application
    Filed: March 1, 2021
    Publication date: September 1, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong
  • Publication number: 20220238674
    Abstract: A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 28, 2022
    Inventors: Qintao ZHANG, Samphy HONG, Lei ZHONG, David Jon LEE, Felix LEVITOV, Carlos CABALLERO, Durgaprasad CHATURVEDULA
  • Patent number: 11387338
    Abstract: A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: July 12, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Qintao Zhang, Samphy Hong, Lei Zhong, David Jon Lee, Felix Levitov, Carlos Caballero, Durgaprasad Chaturvedula
  • Publication number: 20220199802
    Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: Qintao Zhang, Wei Zou, Samphy Hong
  • Publication number: 20220199806
    Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong, Wei Zou, Lei Zhong, David J. Lee, Felix Levitov