Patents by Inventor Samrat Dey

Samrat Dey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Input driven self-clocked dynamic comparator
    Patent number: 11909401
    Abstract: An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT?) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT? signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: February 20, 2024
    Assignee: University of Washington
    Inventors: Samrat Dey, Thomas Lewellen, Jacques Christophe Rudell
  • INPUT DRIVEN SELF-CLOCKED DYNAMIC COMPARATOR
    Publication number: 20230336168
    Abstract: An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT?) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT? signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.
    Type: Application
    Filed: October 9, 2020
    Publication date: October 19, 2023
    Applicant: University of Washington
    Inventors: Samrat Dey, Thomas Lewellen, Jacques Christophe Rudell