Abstract: A method, a phase shifter, and a user equipment (UE) are disclosed for transmitting and receiving signals in a phased array. The method includes receiving, by a balun of a phase shifter, a transmission single-ended input signal at a single-ended side of the balun and generating a transmission differential input signal at a differential side of the balun, generating, by a differential quadrature coupler of the phase shifter, a transmission in-phase signal and a transmission quadrature signal, based on the transmission differential input signal, and combining, by a differential attenuator of the phase shifter, the transmission in-phase signal and the transmission quadrature signal into a differential phase-shifted output signal.

Abstract: An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT?) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT? signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.

Abstract: An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT?) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT? signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.