Patents by Inventor Samriddh BHALLA

Samriddh BHALLA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS AND APPARATUS TO CALIBRATE VOLTAGE-TO-DELAY CONVERSIONS
    Publication number: 20260230045
    Abstract: An example apparatus includes: first amplifier circuitry having a first output and a second output; second amplifier circuitry having an output; first transistor circuitry having a first terminal and a control terminal; second transistor circuitry having a first terminal and a control terminal, the control terminal of the second transistor circuitry coupled to the output of the second amplifier circuitry and the control terminal of the first transistor circuitry; and voltage-to-delay circuitry having a first input and a second input, the first input of the voltage-to-delay circuitry coupled to the first output of the first amplifier circuitry and the first terminal of the first transistor circuitry, the second input of the voltage-to-delay circuitry coupled to the second output of the first amplifier circuitry and the first terminal of the second transistor circuitry.
    Type: Application
    Filed: January 31, 2025
    Publication date: August 6, 2026
    Inventors: Sai Vikas Kandimalla, Neeraj Shrivastava, Samriddh Bhalla, Ashwin Ravi, Shivam Srivastava
  • METASTABILITY ERROR DETECTION AND BER IMPROVEMENT TECHNIQUE IN PIPELINED ADCS
    Publication number: 20260081613
    Abstract: In an example, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to an output of the flash ADC, and a first amplifier having an input coupled to an output of the DAC and the sampling switch. The main path includes a second stage coupled to the first stage and an input of a second amplifier. The main path also includes a backend ADC having an input coupled to an output of the second amplifier. The auxiliary path includes a plurality of metastability comparators coupled to the flash ADC.
    Type: Application
    Filed: November 25, 2025
    Publication date: March 19, 2026
    Inventors: Neeraj SHRIVASTAVA, Visvesvaraya Appala PENTAKOTA, Sai Vikas KANDIMALLA, Samriddh BHALLA, Abhijith N, Prabhansh PANDEY
  • Metastability error detection and BER improvement technique in pipelined ADCs
    Patent number: 12483259
    Abstract: In an example, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to an output of the flash ADC, and a first amplifier having an input coupled to an output of the DAC and the sampling switch. The main path includes a second stage coupled to the first stage and an input of a second amplifier. The main path also includes a backend ADC having an input coupled to an output of the second amplifier. The auxiliary path includes a plurality of metastability comparators coupled to the flash ADC.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: November 25, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Neeraj Shrivastava, Visvesvaraya Appala Pentakota, Sai Vikas Kandimalla, Samriddh Bhalla, Abhijith N, Prabhansh Pandey
  • METASTABILITY ERROR DETECTION AND BER IMPROVEMENT TECHNIQUE IN PIPELINED ADCS
    Publication number: 20250183906
    Abstract: In an example, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to an output of the flash ADC, and a first amplifier having an input coupled to an output of the DAC and the sampling switch. The main path includes a second stage coupled to the first stage and an input of a second amplifier. The main path also includes a backend ADC having an input coupled to an output of the second amplifier. The auxiliary path includes a plurality of metastability comparators coupled to the flash ADC.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 5, 2025
    Inventors: Neeraj SHRIVASTAVA, Visvesvaraya Appala PENTAKOTA, Sai Vikas KANDIMALLA, Samriddh BHALLA, Abhijith N, Prabhansh PANDEY