Patents by Inventor Samridh Jaiswal

Samridh Jaiswal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133977
    Abstract: In one aspect, a method of manufacturing a magnetoresistance (MR) element having layers include ramping up a temperature of a reference layer of the MR element to an annealing temperature of the reference layer by increasing an amplitude of laser pulses applied to the reference layer over time to an amplitude that corresponds to the annealing temperature of the reference layer; applying a magnetic field to the reference layer; and maintaining the amplitude of subsequent laser pulses over time that have the amplitude that corresponds to the annealing temperature of the reference layer until at least the reference layer is annealed.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 25, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Samridh Jaiswal, Paolo Campiglio, Sundar Chetlur
  • Publication number: 20240085463
    Abstract: In one aspect, a sensor includes a first metal layer portion and a second metal layer portion separated by an insulator material; a conductive material layer in electrical contact with the first metal layer portion and the second metal layer portion; and a tunnel magnetoresistance (TMR) element positioned on and in electrical contact with the conductive material layer. A first current is configured to flow from the first metal layer portion, through the conductive material layer, to the second metal layer portion, and a second current is configured to flow from the first metal layer portion, through the conductive material layer, through the TMR element, and exiting through a top of the TMR element.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Samridh Jaiswal, Paolo Campiglio, Sundar Chetlur, Maxim Klebanov, Yen Ting Liu
  • Publication number: 20240074322
    Abstract: In one aspect, a method includes depositing magnetoresistance (MR) layers of a MR element on a semiconductor structure; depositing a first hard mask on the MR layers; depositing and patterning a first photoresist on the first hard mask using photolithography to expose portions of the first hard mask; etching the exposed portions of the first hard mask; etching a portion of the MR layers using the first hard mask; depositing a second hard mask on a first capping layer; depositing and patterning a second photoresist on the second hard mask using photolithography to expose portions of the second hard mask; etching the exposed portions of the second hard mask; etching the MR element using the second hard mask; etching portions of the first hard mask down to a top MR layer of the MR element; and depositing a conducting material on the top MR layer to form an electroconductive contact.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Maxim Klebanov, Yen Ting Liu, Sundar Chetlur, Paolo Campiglio, Samridh Jaiswal
  • Publication number: 20240027547
    Abstract: Methods and apparatus for a magnetoresistive (MR) sensor a free layer with a thickness of the CoFeB material to produce out-of-plane sensing for the sensor and a reference layer magnetically coupled to the free layer. A dusting layer of an oxide material is disposed on the free layer to achieve perpendicular magnetic anisotropy for an interface of the oxide layer and the free layer for a desired sensitivity for the sensor.
    Type: Application
    Filed: July 19, 2022
    Publication date: January 25, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Samridh Jaiswal, Paolo Campiglio
  • Patent number: 11719771
    Abstract: Methods and apparatus for a magnetoresistive (MR) sensor including a seed layer having a CoFe layer for canceling hysteresis in the MR sensor. The MR stackup can include a free layer and a reference layer. The seed layer having CoFe provides a desired texturing of the stackup to cancel hysteresis effects.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: August 8, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventors: Paolo Campiglio, Samridh Jaiswal, Yen Ting Liu, Maxim Klebanov, Sundar Chetlur