Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for ESYNC hybrid mode. A processor determines that an AP is to transition from a first power mode to a second power mode based on a change in a refresh rate of a display panel. The processor switches, based on the determination and during a transmission of a continuous external HSYNC signal, a source of a clock associated with the external HSYNC signal from being generated via PLL clock to being generated via an RC oscillator clock.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a power efficient display architecture. A display processor may obtain an indication that UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The display processor may drive a first display via a first controller of a first DPU based on the indication. The display processor may drive a second display via a controller of a second DPU if the UC is to be displayed at the first resolution, or drive the second display via a second controller of the first DPU if the UC is to be displayed at the second resolution.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a power efficient display architecture. A display processor may obtain an indication that UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The display processor may drive a first display via a first controller of a first DPU based on the indication. The display processor may drive a second display via a controller of a second DPU if the UC is to be displayed at the first resolution, or drive the second display via a second controller of the first DPU if the UC is to be displayed at the second resolution.

Abstract: A method, an apparatus, and a computer-readable medium for displaying a blinking cursor are provided in a power-efficient manner. Various hardware and protocol command enhancements are provided allowing a visible cursor frame region and an invisible cursor frame region are sequentially displayed creating the blinking cursor effect. Further support is provided for compressed frames, for example, frames compressed with the VESA Display Stream Compression (DSC) standard.