Abstract: A display system includes a repairable memory that re-routes data when a defect exists in the memory. A significant bit in the display memory that would otherwise be corrupted by a bad memory cell is re-routed to a least significant bit position in the memory, and the least significant information is discarded. The repairable memory includes a memory device and two repair routers. One repair router is on the input of the memory, and one repair router is on the output of the memory. One or more least significant bits can be sacrificed to preserve more significant bit information.

Abstract: In some embodiments, a drive circuit may be coupled to a spatial light modulator, wherein the drive circuit provides a non-linear analog ramp signal to the spatial light modulator. Other embodiments are disclosed and claimed.

Abstract: Some embodiments provide application, at a beginning of a first display frame, of a first potential to a pixel imaging element, the first potential to reset the pixel imaging element to a reset state, application, during the first display frame, of a second potential to the pixel imaging element, the second potential to set the pixel imaging element to a desired imaging state, and change, at a beginning of a second display frame subsequent to the first display frame, of the second potential to a third potential, the third potential to reset the pixel imaging element to the reset state.

Abstract: An LCOS chip may have a pixel divided into an outer subpixel and an inner subpixel. A driver may independently drive the subpixels. The driving technique may be pulse-width modulation. Because of the pixel is divided into subpixels, pulses of short widths that drive an undivided pixel may be replaced with pulses of longer duration. In an alternative embodiment, the pixel is not divided into subpixels. The driving technique may be a combination of pulse width and pulse height modulation. The waveform may replace pulses of short widths with pulses of longer duration and reduced voltage levels.

Abstract: A negative bias voltage may be utilized to bias a spatial light modulator and to enable the spatial light modulator to be modulated using relatively low supply voltages. During the negative frame, a positive bias voltage may be utilized and during the positive frame, a negative bias voltage may be utilized. This avoids damage to the liquid crystal material. The necessary modulating voltages may be within the range available from leading edge silicon technologies.

Abstract: Some embodiments provide application, at a beginning of a first display frame, of a first potential to a pixel imaging element, the first potential to reset the pixel imaging element to a reset state, application, during the first display frame, of a second potential to the pixel imaging element, the second potential to set the pixel imaging element to a desired imaging state, and change, at a beginning of a second display frame subsequent to the first display frame, of the second potential to a third potential, the third potential to reset the pixel imaging element to the reset state.

Abstract: A digital driver formed a liquid crystal uses a pseudo static memory cell formed of two transistors to hold the charge that will be applied to the different parts of the liquid crystal. The pseudo static memory is formed of two transistors, one of which is a pass transistor which passes the digital value and then goes into a high impedance date. The other transistor is a transistor configured to use its gate capacitance to store the charge. When the charge is above a specified level, it acts like a digital one and turns on the transistor. Conversely, when the charge is below level, it acts like a digital zero, turning off the transistor.

Abstract: A negative bias voltage may be utilized to bias a spatial light modulator and to enable the spatial light modulator to be modulated using relatively low supply voltages. During the negative frame, a positive bias voltage may be utilized and during the positive frame, a negative bias voltage may be utilized. This avoids damage to the liquid crystal material while reducing the necessary modulating voltages to within the range available from leading edge silicon technologies.

Abstract: An LCOS chip may have a pixel divided into an outer subpixel and an inner subpixel. A driver may independently drive the subpixels. The driving technique may be pulse-width modulation. Because of the pixel is divided into subpixels, pulses of short widths that drive an undivided pixel may be replaced with pulses of longer duration. In an alternative embodiment, the pixel is not divided into subpixels. The driving technique may be a combination of pulse width and pulse height modulation. The waveform may replace pulses of short widths with pulses of longer duration and reduced voltage levels.

Abstract: A digital driver formed a liquid crystal uses a pseudo static memory cell formed of two transistors to hold the charge that will be applied to the different parts of the liquid crystal. The pseudo static memory is formed of two transistors, one of which is a pass transistor which passes the digital value and then goes into a high impedance date. The other transistor is a transistor configured to use its gate capacitance to store the charge. When the charge is above a specified level, it acts like a digital one and turns on the transistor. Conversely, when the charge is below level, it acts like a digital zero, turning off the transistor.

Abstract: A processor has a clock generator circuit, a sleep pin that receives an external sleep signal, and a first interface circuit coupled to the clock generator circuit and the sleep pin. The clock generator circuit generates a core clock signal and a bus clock signal in response to an external clock signal. When the external sleep signal is asserted, the processor enters a sleep state when the core clock signal and the bus clock signal are in a first predetermined relationship with each other.

Abstract: A CMOS delay cell with feedback circuitry to ensure that the delay cell is operating in saturation mode. A voltage controlled oscillator (VCO) comprising a loop of an odd number of delay cells, where the VCO is operating in a saturation mode. Under normal operation any intermediate node in the VCO will generate an output signal from a delay cell with reduced supply noise. The output signal can be used to generate a PLL clock signal with a lower phase jitter than prior art VCO's operating at low supply potentials.

Abstract: A read signal and write signal for a FIFO each has a flag generating edge and a preceding edge. The read or write counter in an empty of full flag generator responds to the preceding edge of the read or write signal so that the empty or full comparator of the generator may generate an updated empty or full flag value before the onset of the flag generating edge. The empty or full flag generator also includes a gate and a pulse generating circuit. The pulse generating circuit responds to the flag generating edge by generating an enabling signal enabling the gate to pass the comparator output to a latch. When the empty or full comparator indicates that a FIFO is empty or full, the comparator output passed by the gate will force the output high, thereby asserting an empty flag or a full flag. The empty flag generator also includes a second pulse generating circuit which updates the empty flag signal to indicate a non-empty FIFO in response to each write signal.

Abstract: To reduce the access time of a FIFO, a storage device is provided for storing pre-loaded data to be read from the memory array of the FIFO. Thus during each read operation, the pre-loaded data in the storage device is read and the next unit of data to be read during the next read operation is pre-loaded from the array into the storage device. A second storage device is provided for storing the first unit of data written into the array after the array is empty. Thus during the first read operation after the array is rendered non-empty by one or more consecutive write operations, the first unit of data stored in the second storage device is read during the first read operation. This avoids reading garbage from the first storage device which is pre-loaded during the last read operation before the FIFO is empty.