Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: A video camera comprises a housing (102) configured of a top housing portion (104), a mid-housing portion (106) and a bottom housing portion (108). The top housing portion is configured as a circular and rounded exterior contoured wall (110) having an exterior recessed feature (112) formed along an edge (114). The mid-housing portion (106) is formed of an IR window ring (116) having an alignment tab (118) extending therefrom, the alignment tab being aligned and recessed within the exterior recessed feature (112) of the rounded exterior contoured wall (110) of the top housing portion (104), and the bottom housing portion (108) providing a camera dome (120) seated within and protruding from the IR window ring (116).

Abstract: The present disclosure provides techniques for presenting a reward impression. A computing system can receive, from a client device, a request to view the reward impression having a first time slot and a second time slot. The computing system can calculate a first conversion rate associated with a first content item being presented in the first time slot and a second conversion rate associated with a second content item being presented in the second time slot. The computing system can select, using the one or more machine-learned models based on the first conversion rate and the second conversion rate, the first content item and the second content item from a plurality of content items. The computing system can cause the presentation of the first content item in the first time slot and the second content item in the second time slot of the reward impression.

Abstract: A semiconductor package includes: a substrate having a metallic surface; a semiconductor die metallurgically bonded to the metallic surface of the substrate by a first solder joint; and a solder wetting structure metallurgically welded to the metallic surface of the substrate outside a perimeter of the semiconductor die and adjacent to one or more side faces of the semiconductor die. Excess solder squeezed out from under the semiconductor die is metallurgically bonded to the solder wetting structure. Methods of producing the semiconductor package and solder wetting structure are also described.

Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: A bond pad connector to be disposed on a stretchable substrate and adapted to secure an electronic component thereon. The bond pad connector includes two spaced apart bond pads that are adapted to be disposed on the stretchable substrate to face each other. Each of the two bond pads is adapted to be connected to a respective conductive trace and includes: a stress relieve component that is adapted to be connected to the conductive trace, the stress relieve component being formed with a central hole; and an extension component extending from the stress relieve component and opposite to the conductive trace. The electronic component is secured onto the bond pad connector by attaching the electronic component to, for each of the bond pads, at least a part of the extension component.

Abstract: A flexible composite substrate for a wearable antenna includes a fabric sheet and a single-layer dielectric film immersed into the fabric sheet. The single-layer dielectric film includes a dielectric resin matrix and a low dielectric loss material which is mixed with the dielectric resin matrix and which serves as a wireless functional dielectric interface material.

Abstract: A rework patch for an electronic circuit includes a flexible patch body and at least two patch traces. The electronic circuit includes a substrate, at least two board traces formed on the substrate, and at least one defect portion within at least one of the board traces. The patch body is attached to the substrate to partially cover each of the board traces and to cover the defect portion. The patch traces are formed on the patch body. A pattern of the patch traces corresponds to a pattern of a portion of the board traces covered by the patch body.

Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Abstract: The present invention relates to a coating comprising a (i) boronic ester of Formula (I) disclosed herein, and (ii) an elastomer, wherein (i) and (ii) are cured with pentaerythritol tetrakis(3-mercaptoptopionate) (PTMP) and 3,6-dioxa-1,8-octanedithiol (DODT).

Abstract: Provided are methods and systems for the production of alkyl polyglucoside. The methods and systems provide for improved purification that results in reduced produce degradation.

Abstract: Disclosed herein are implementations of methods and devices for stacking printed circuit board (PCB) assemblies (PCBA) with a single reflow process which decreases impact on surface mount technology (SMT) component and solder joint reliability.

Abstract: Provided are personal care compositions comprising ester polyol esters, ester polyol esters, manufacturing methods thereof, and the use of ester polyol esters in personal care compositions.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for debugging an application are provided. In some aspects, a method includes detecting rendering of a digital component by an application executing on the device. A first signals indicative of visible attributes of content assets of the test digital component and second signals indicative of hierarchical associations between the content assets as rendered are obtained. A validation process the compares the first signals and the second signals to a set of requirements is invoked. A determination is made that one or more requirements are not met by the first signals or the second signals. In response to determining that the one or more requirements are not met a non-compliant overlay is provided within the application indicating that the digital component fails to comply with the one or more requirements.

Abstract: A video camera comprises a housing (102) configured of a top housing portion (104), a mid-housing portion (106) and a bottom housing portion (108). The top housing portion is configured as a circular and rounded exterior contoured wall (110) having an exterior recessed feature (112) formed along an edge (114). The mid-housing portion (106) is formed of an IR window ring (116) having an alignment tab (118) extending therefrom, the alignment tab being aligned and recessed within the exterior recessed feature (112) of the rounded exterior contoured wall (110) of the top housing portion (104), and the bottom housing portion (108) providing a camera dome (120) seated within and protruding from the IR window ring (116).

Abstract: An electronic circuit, comprising: an integrated substrate structure comprising one or more electrically conductive traces comprising plating on a laser-etched, non-conductive isolated portion of the integrated substrate structure defining each electrically conductive trace; one or more electrically conductive pads at one or more predetermined positions along the one or more electrically conductive traces; and an electrical component surface mounted to the at least one electrically conductive pad with interconnect and bonding material.

Abstract: A video camera comprises a housing (102) configured of a top housing portion (104), a mid-housing portion (106) and a bottom housing portion (108). The top housing portion is configured as a circular and rounded exterior contoured wall (110) having an exterior recessed feature (112) formed along an edge (114). The mid-housing portion (106) is formed of an IR window ring (116) having an alignment tab (118) extending therefrom, the alignment tab being aligned and recessed within the exterior recessed feature (112) of the rounded exterior contoured wall (110) of the top housing portion (104), and the bottom housing portion (108) providing a camera dome (120) seated within and protruding from the IR window ring (116).

Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.