Abstract: In a microprocessor system provided with a central processing unit with an internal address and data bus arrangement connected to the central processing unit and to an operation codes memory (ROM) the clock of an external serial bus is obtained from connection to the least significant bit wire of the internal address bus. The central processing unit is operated in such a way that the addresses carried by the address bus, during an operation of writing on the external serial bus, are regularly incremented by unity, producing in the least significant bit wire a sequence of alternating ONES and ZEROS. For this purpose, the operation codes memory contains, in the locations corresponding to the addresses present on the internal address bus during a write operation, operation codes intended to establish the value of the datum on a port of the central processing unit to which the data wire of the external serial bus is connected.