Patents by Inventor Samuel Broydo
Samuel Broydo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070080414Abstract: An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.Type: ApplicationFiled: September 18, 2006Publication date: April 12, 2007Applicant: Applied Materials, Inc.Inventors: Claes Bjorkman, Lawrence West, Dan Maydan, Samuel Broydo
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Patent number: 7110629Abstract: An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.Type: GrantFiled: July 21, 2003Date of Patent: September 19, 2006Assignee: Applied Materials, Inc.Inventors: Claes Bjorkman, Lawrence C. West, Dan Maydan, Samuel Broydo
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Patent number: 7072534Abstract: An article of manufacture comprising an optical ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.Type: GrantFiled: October 25, 2002Date of Patent: July 4, 2006Assignee: Applied Materials, Inc.Inventors: Claes Björkman, Lawrence C. West, Dan Maydan, Samuel Broydo
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Patent number: 7043106Abstract: An optical ready substrate made at least in part of a first semiconductor material and having a front side and a backside, the front side having a top surface that is of sufficient quality to permit microelectronic circuitry to be fabricated thereon using semiconductor fabrication processing techniques. The optical ready substrate includes an optical signal distribution circuit fabricated on the front side of the substrate in a first layer region beneath the top surface of the substrate. The optical signal distribution circuit is made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuitry to be fabricated thereon.Type: GrantFiled: October 25, 2002Date of Patent: May 9, 2006Assignee: Applied Materials, Inc.Inventors: Lawrence C. West, Claes Björkman, Dan Maydan, Samuel Broydo
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Publication number: 20050072979Abstract: An optical-ready substrate made at least in part of a first semiconductor material and having a front side and a backside, the front side having a top surface that is of sufficient quality to permit microelectronic circuitry to be fabricated thereon using semiconductor fabrication processing techniques. The optical-ready substrate includes an optical signal distribution circuit fabricated on the front side of the substrate in a first layer region beneath the top surface of the substrate. The optical signal distribution circuit is made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuitry to be fabricated thereon.Type: ApplicationFiled: July 21, 2003Publication date: April 7, 2005Inventors: Lawrence West, Dan Maydan, Samuel Broydo, Claes Bjorkman
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Publication number: 20040114853Abstract: An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.Type: ApplicationFiled: July 21, 2003Publication date: June 17, 2004Applicant: APPLIED MATERIALS, INC.Inventors: Claes Bjorkman, Lawrence C. West, Dan Maydan, Samuel Broydo
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Publication number: 20040013338Abstract: An article of manufacture comprising an optical ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.Type: ApplicationFiled: October 25, 2002Publication date: January 22, 2004Applicant: Applied Materials, Inc.Inventors: Claes Bjorkman, Lawrence C. West, Dan Maydan, Samuel Broydo
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Publication number: 20040012041Abstract: An optical ready substrate made at least in part of a first semiconductor material and having a front side and a backside, the front side having a top surface that is of sufficient quality to permit microelectronic circuitry to be fabricated thereon using semiconductor fabrication processing techniques. The optical ready substrate includes an optical signal distribution circuit fabricated on the front side of the substrate in a first layer region beneath the top surface of the substrate. The optical signal distribution circuit is made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuitry to be fabricated thereon.Type: ApplicationFiled: October 25, 2002Publication date: January 22, 2004Applicant: Applied Materials, Inc.Inventors: Lawrence C. West, Claes Bjorkman, Dan Maydan, Samuel Broydo
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Patent number: 6548396Abstract: A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.Type: GrantFiled: June 5, 2001Date of Patent: April 15, 2003Assignee: Applied Materials, Inc.Inventors: Mehul Naik, Samuel Broydo
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Patent number: 6514671Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).Type: GrantFiled: September 29, 2000Date of Patent: February 4, 2003Assignee: Applied Materials, Inc.Inventors: Suketu A. Parikh, Mehul B. Naik, Samuel Broydo, H. Peter W. Hey
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Publication number: 20020048929Abstract: A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.Type: ApplicationFiled: June 5, 2001Publication date: April 25, 2002Applicant: Applied Materials, Inc.Inventors: Mehul Naik, Samuel Broydo
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Patent number: 6245662Abstract: A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.Type: GrantFiled: July 23, 1998Date of Patent: June 12, 2001Assignee: Applied Materials, Inc.Inventors: Mehul Naik, Samuel Broydo
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Patent number: 5689133Abstract: An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp.Type: GrantFiled: September 9, 1996Date of Patent: November 18, 1997Assignee: Xilinx, Inc.Inventors: Sheau-Suey Li, Randy T. Ong, Samuel Broydo, Khue Duong
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Patent number: 5646814Abstract: A multi-electrode electrostatic chuck (20) for holding a substrate (42) such as a silicon wafer during processing is described. The electrostatic chuck (20) comprises (i) a first electrode (22), (ii) a second electrode (24), and (iii) an insulator (26) having a lower portion (26a), a middle portion (26b) and an upper portion (26c). The lower portion (26a) of the insulator (26) is below the first electrode (22) and has a bottom surface (28) suitable for resting the chuck (20) on a support (44) in a process chamber (41). The middle portion (26b) of the insulator (26) lies between the first and second electrodes (22), (24). The upper portion (26c) of the insulator (26) is on the second electrode (24), and has a top surface (30) suitable for holding a substrate (42). The first and second electrodes (22, 24) can have a unipolar or bipolar configurations. In operation, the chuck (20) is placed on a support (44) in a process chamber (41) so that the bottom surface (28) of the chuck (20) rests on the support (44).Type: GrantFiled: July 15, 1994Date of Patent: July 8, 1997Assignee: Applied Materials, Inc.Inventors: Shamouil Shamouilian, Samuel Broydo, Manoocher Birang
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Patent number: 5623387Abstract: An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp.Type: GrantFiled: June 5, 1995Date of Patent: April 22, 1997Assignee: XILINX, Inc.Inventors: Sheau-Suey Li, Randy T. Ong, Samuel Broydo, Khue Duong
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Patent number: 5477414Abstract: An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp.Type: GrantFiled: May 3, 1993Date of Patent: December 19, 1995Assignee: Xilinx, Inc.Inventors: Sheau-Suey Li, Randy T. Ong, Samuel Broydo, Khue Duong