Patents by Inventor Samuel C. Ramac
Samuel C. Ramac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7714366Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.Type: GrantFiled: November 16, 2004Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Patent number: 6893948Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: GrantFiled: July 11, 2003Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Patent number: 6787427Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.Type: GrantFiled: October 1, 2003Date of Patent: September 7, 2004Assignee: International Business Machines CorporationInventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
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Publication number: 20040063293Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.Type: ApplicationFiled: October 1, 2003Publication date: April 1, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
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Publication number: 20040023476Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: ApplicationFiled: July 11, 2003Publication date: February 5, 2004Applicant: International Business MachinesInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Patent number: 6670263Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: GrantFiled: March 10, 2001Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Patent number: 6656809Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.Type: GrantFiled: January 15, 2002Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
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Publication number: 20030132453Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.Type: ApplicationFiled: January 15, 2002Publication date: July 17, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
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Publication number: 20020155665Abstract: A field effect transistor device has a semiconductor substrate having a predetermined impurity concentration of a first conductivity type. Inpurity layers of a second conductivity type are formed spaced apart at the main surface of the semiconductor substrate. The impurity layers make up source/drain regions. A region between the impurity layers defines a channel region. A notch-shaped conductive layer is formed on the channel region. The notch-shaped conductive layer has an upper layer section longer than a lower layer section. The upper and lower layer sections are formed of at least two different materials, one being silicon-germanium layer with varying germanium content. The material of the lower layer section can be etched at a greater rate than the material of the upper layer section during a common etching process.Type: ApplicationFiled: April 24, 2001Publication date: October 24, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION,Inventors: Bruce B. Doris, Kevin M. Houlihan, Samuel C. Ramac
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Publication number: 20020149064Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: ApplicationFiled: March 10, 2001Publication date: October 17, 2002Inventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glenn L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Patent number: 5899724Abstract: According to the preferred embodiment of the present invention, an improved resistor and method of fabrication is provided. The method for fabricating a resistive element into an integrated circuit semiconductor device comprises the steps of: depositing a dielectric film, such as silicon nitride; depositing a titanium film upon the dielectric film; and annealing the titanium and dielectric films. This causes titanium to be diffused into the dielectric film. This creates a resistive element having a relatively high resistivity. The preferred embodiment method has the advantage of being easily integrated into conventional integrated circuit fabrication techniques.Type: GrantFiled: May 9, 1996Date of Patent: May 4, 1999Assignees: International Business Machines Corporation, Siemens AktiengesellschaftInventors: David Mark Dobuzinsky, Stephen Gerard Fugardi, Erwin Hammerl, Herbert Lei Ho, Samuel C. Ramac, Alvin Wayne Strong
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Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures
Patent number: 5747866Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. for 60 seconds.Type: GrantFiled: January 21, 1997Date of Patent: May 5, 1998Assignee: Siemens AktiengesellschaftInventors: Herbert Ho, Erwin Hammerl, David M. Dobuzinsky, Herbert Palm, Stephen Fugardi, Atul Ajmera, James F. Moseman, Samuel C. Ramac -
Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures
Patent number: 5643823Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. C. for 60 seconds.Type: GrantFiled: September 21, 1995Date of Patent: July 1, 1997Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Herbert Ho, Erwin Hammerl, David M. Dobuzinsky, J. Herbert Palm, Stephen Fugardi, Atul Ajmera, James F. Moseman, Samuel C. Ramac