Patents by Inventor Samuel David AHEARN

Samuel David AHEARN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791713
    Abstract: Described herein is a method of cooling a plurality of power devices, where the power devices are arranged as a plurality of switches used to generate a three-phase output AC voltage. Based on power device stress data, one or more switches (associated with one or more phase output AC voltages) may be identified as requiring more cooling than other of the switches. The switches are controlled to apply a common mode component voltage to each of the three phases for at least a portion of one or more output AC voltage segments. The common mode component voltage has a maximum amplitude that is sufficient to clamp the phase AC output voltage of the identified phase(s) to the positive supply rail voltage and/or negative rail supply voltage when the respective phase AC voltage is approaching respectively the positive supply rail voltage or negative supply rail voltage to cool the identified switch(es).
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: October 17, 2023
    Assignee: YASA LIMITED
    Inventors: Simon David Hart, Samuel David Ahearn
  • Patent number: 11757374
    Abstract: We describe techniques to reduce DC ripple voltage in an inverter by determining a plurality of switching events for each of the three phases in each Pulse Width Modulation (PWM) period. The switching events provide a desired target output voltage for the respective PWM period. From this determination of the switching events, a comparison can be made to determine a first time period between a first and second switching event across all of the phases, and a second time period between the second and a third switching event across all of the phases. The timing of one or more switching events in only one of the phases in the respective PWM period is adjusted in response to the determined time period being greater than a threshold in order to reduce the determined first or second time period.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: September 12, 2023
    Assignee: YASA LIMITED
    Inventors: Simon David Hart, Samuel David Ahearn, Richard Phillips, Tim Woolmer
  • Patent number: 11646676
    Abstract: A modulation technique is described in which a controller modulates the output AC voltages to introduce an offset to the phase that is most positive or most negative such that the phase is clamped to the +dc supply when the respective phase is most positive and to the ?dc supply rail when most negative. The offset is provided by introducing a common mode component voltage to all of the phases over a plurality of output angle segments. In order to reduce the Noise Vibration and Harshness (NVH) and EMI, the common mode component voltage amplitude is varied over the output angles within the respective segment between a minimum and a maximum in order to control a slew rate of the rising or falling edges of the three phase AC output voltages.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: May 9, 2023
    Assignee: YASA LIMITED
    Inventors: Simon David Hart, Samuel David Ahearn
  • Publication number: 20220200442
    Abstract: Described herein is a method of cooling a plurality of power devices, where the power devices are arranged as a plurality of switches used to generate a three-phase output AC voltage. Based on power device stress data, one or more switches (associated with one or more phase output AC voltages) may be identified as requiring more cooling than other of the switches. The switches are controlled to apply a common mode component voltage to each of the three phases for at least a portion of one or more output AC voltage segments. The common mode component voltage has a maximum amplitude that is sufficient to clamp the phase AC output voltage of the identified phase(s) to the positive supply rail voltage and/or negative rail supply voltage when the respective phase AC voltage is approaching respectively the positive supply rail voltage or negative supply rail voltage to cool the identified switch(es).
    Type: Application
    Filed: December 22, 2021
    Publication date: June 23, 2022
    Inventors: Simon David HART, Samuel David AHEARN
  • Publication number: 20220200436
    Abstract: A modulation technique is described in which a controller modulates the output AC voltages to introduce an offset to the phase that is most positive or most negative such that the phase is clamped to the +dc supply when the respective phase is most positive and to the ?dc supply rail when most negative. The offset is provided by introducing a common mode component voltage to all of the phases over a plurality of output angle segments. In order to reduce the Noise Vibration and Harshness (NVH) and EMI, the common mode component voltage amplitude is varied over the output angles within the respective segment between a minimum and a maximum in order to control a slew rate of the rising or falling edges of the three phase AC output voltages.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 23, 2022
    Inventors: Simon David HART, Samuel David AHEARN
  • Publication number: 20220166346
    Abstract: We describe techniques to reduce DC ripple voltage in an inverter by determining a plurality of switching events for each of the three phases in each Pulse Width Modulation (PWM) period. The switching events provide a desired target output voltage for the respective PWM period. From this determination of the switching events, a comparison can be made to determine a first time period between a first and second switching event across all of the phases, and a second time period between the second and a third switching event across all of the phases. The timing of one or more switching events in only one of the phases in the respective PWM period is adjusted in response to the determined time period being greater than a threshold in order to reduce the determined first or second time period.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 26, 2022
    Inventors: Simon David HART, Samuel David AHEARN, Richard PHILLIPS, Tim WOOLMER