Abstract: A sequential memory device having a read pipeline data structure for reading data from a bitline of a memory array of the device is disclosed. The read pipeline data structure includes at least one data path including a sense amp for sensing the logic level appearing on the bitline, a flip-flop for providing an output signal indicative of the data bits received on the bitline, and means for initializing the data path upon power up of the device such that the first data bit from the memory array is available for output from the device without the need and before the occurrence of a clock signal.

Abstract: An I.sup.2 C bus-compatible, serial EEPROM device is used in applications involving storage and serial transmission of configuration and control information for an intelligent peripheral device with which the EEPROM device is associated, for communication on a bus to a host device adapted to control the peripheral device. The EEPROM device has a memory array for storing data representing the configuration and control information. Two modes of data transmission are supported by the EEPROM device, and are alternately and selectively established according to whether data stored in the EEPROM array is to be read only, by sequential output onto the bus, or the array is also to be allowed to be written to. The arrangement ultimately allows intelligent interaction between the host device and the peripheral device. A separate clock line supplements the usual clock line and data line of an I.sup.2 C bus to support the distinct and different modes, with clocking by the respective clock line for the established mode.

Abstract: A serial EEPROM (electrically erasable programmable read only memory) device and method for reducing the time required to load data into the serial EEPROM device using a special write cache are disclosed. The EEPROM has an internal memory array for receiving a burst of data sent by a microcontroller. Data in the burst of data is initially loaded into an SRAM (static random access memory) write cache where it is stored sequentially and grouped in a plurality of pages, so that the bus and the microcontroller are freed to allow the microcontroller to perform other processing tasks at least until the EEPROM memory is written and the EEPROM is again accessible to the microcontroller. Writing of the internal memory array is accomplished sequentially with data from the pages of the cache loaded into rows of the internal memory array until the cache is depleted, the pages being sized so that an integral number of pages is stored in each row of the internal memory array.

Abstract: Power consumption of a serial EEPROM is reduced while simultaneously precluding data corruption during write operations. These results are achieved by operating a brownout detector in the device to sense EEPROM supply voltage below a predetermined level and thereupon to place the EEPROM in a reduced power mode, but only during an interval that a write sequence is taking place. Such an interval includes loading of data in a temporary storage cache and writing the loaded data into the EEPROM. At the same time that the low voltage level is detected during a write sequence, any load or write operation then in progress is aborted. The brownout detector is intentionally left disabled or in a sleep mode during any read mode or standby mode since there is no jeopardy of corrupting the EEPROM memory during those times.

Abstract: An erasable programmable memory device has a number of data storage blocks. Each block has an endurance characteristic that at least roughly defines the number of times data may be erased from and written to the block before it wears out in that data cannot then be further erased from and written to the block. A redundant data storage block of memory capacity and endurance similar to that of each of the other data storage blocks is disposed in parallel with a selected one of the latter for which higher endurance is desired. This enables identical data to be written simultaneously to the two blocks and thus considerably increases the endurance of the selected block by virtue of the fact that identical memory cells in both blocks must fail before the endurance of the selected block will be depleted. After the selected block has been designated for high endurance and placed in parallel with the redundant block, a fuse may be set to prevent alteration of that designation.

Abstract: An erasable programmable memory device has a number of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereafter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write protection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by comparing each write operation address with the addresses of the data storage cells encompassed within the protected area, and if it is within that area, aborting the write operation.

Abstract: The usability of an electrically erasable programmable semiconductor memory device is assured after shipment from the factory despite implementing the device with a user option to selectively configure the security, endurance, organization, density or protocol of the memory array of the device. The user selected configuration is made permanent and inaccessible for change by programming associated normally reversible configuration fuses which are rendered incapable of being reprogrammed (reversed) thereafter by the automatic and simultaneous programming of a lockout fuse.

Abstract: An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the end of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally caused by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors is controlled by controlling the voltage on the gate or base of the transistor which is providing the particular logic state. This control is responsive to the magnitude of the power supply voltage. An impedance which varies in resistance with supply voltage is placed in series between the positive power supply terminal and the gate or base of the output transistors.

Abstract: In a static random access memory in which the array is comprised of MOS transistors and at least some of the peripheral circuits are comprised of bipolar transistors, the bit lines and data lines are precharged to a base to emitter voltage drop (i.e. one Vbe) below the positive power supply voltage. This increases cell stability. Additionally, Vbe varies comparatively little over process. Additionally, precharging the bit lines and data lines to a Vbe below the positive power supply voltage allows for the use of a high speed bipolar differential amplifier in its optimum operating range as the first stage sense amplifier.