Abstract: An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Abstract: An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Abstract: A method for selectively inverting a word to be written to a memory is provided. The memory includes memory cells, each memory cell allowing at least two values associated with at least one bit to be stored, the decision as to whether to invert a word being made depending on a number of vulnerable values, which number is determined on the basis of the data bits, of the inversion bit and of uneven check bits.

Abstract: A method for selectively inverting a word to be written to a memory is provided. The memory includes memory cells, each memory cell allowing at least two values associated with at least one bit to be stored, the decision as to whether to invert a word being made depending on a number of vulnerable values, which number is determined on the basis of the data bits, of the inversion bit and of uneven check bits.

Abstract: A method is provided for generating a maximized linear correcting code from a base linear correcting code, the base correcting code and the maximized linear correcting code being associated with one and the same parity matrix H, the matrix being used to generate syndromes, the syndromes being used for decoding code words. The method comprises a step of identifying the syndromes unused for decoding the base linear correcting code, a step of identifying the errors that can affect the code words and make it possible to obtain the unused syndromes when a code word is multiplied by the matrix H and a step of selecting a unique error for each unused syndrome from among the identified errors, the error being called additional error.

Abstract: A device for correcting an initial binary word affected by an error in 1 or 2 bits and arising from a corrector code endowed with a minimum Hamming distance of 3 or 4, comprises first means for correcting an error of 1 bit and for detecting an error of more than 1 bit in the initial word and second means for correcting an error of 1 bit in a word arising from an inversion module, able to receive a datum indicative of a binary level of confidence, low or high, assigned to each of the bits of at least one part of the initial word, said inversion module being configured to invert the bits of the initial word which suffer the low confidence level, and a multiplexer with at least two inputs which is driven by the means for detecting an error of more than 1 bit in the initial word, said multiplexer being fed on a first input by the output of the first correction means and on a second input by the output of the second correction means.

Abstract: A scan sequential element device for an integrated circuit receiving three input signals, at least one clock signal as input, and an output comprises: a system sequential element including an input controlled by a first input signal of the device, an input controlled by a second input signal of the device, and an input controlled by one of the clock signals received as input by the device, and a shadow sequential element including an input controlled by the third input signal of the device, an input controlled by the second input signal of the device, and an input controlled by one of said clock signals received as input by the device, the device being configured so the first input signal is propagated to the output of the device through the system sequential element when the second input signal is disabled, and the third input signal is propagated to the output of the device through the shadow sequential element and the system sequential element when the second input signal is enabled, the propagation of the

Abstract: A method for determining the erroneous bits in an initial binary word affected by a double error and arising from a code endowed with a minimum Hamming distance equal to 3 or 4 comprises reception of a datum indicative of a binary level of confidence, low or high, assigned to each of the bits of at least one part of the initial word, a step of generating the syndrome on the basis of the initial word and a step of determining whether the syndrome is that of a code word affected by a double error, in which if it identifies, on the basis of the syndrome, an error in the initial word whose two affected bits correspond to bits of low confidence in the initial word, the two erroneous bits are selected to be corrected. The method applies notably to the fields of error correcting codes and nanometric technologies.

Abstract: A device for correcting an initial binary word affected by an error in 1 or 2 bits and arising from a corrector code endowed with a minimum Hamming distance of 3 or 4, comprises first means for correcting an error of 1 bit and for detecting an error of more than 1 bit in the initial word and second means for correcting an error of 1 bit in a word arising from an inversion module, able to receive a datum indicative of a binary level of confidence, low or high, assigned to each of the bits of at least one part of the initial word, said inversion module being configured to invert the bits of the initial word which suffer the low confidence level, and a multiplexer with at least two inputs which is driven by the means for detecting an error of more than 1 bit in the initial word, said multiplexer being fed on a first input by the output of the first correction means and on a second input by the output of the second correction means.

Abstract: A method is provided for generating a maximized linear correcting code from a base linear correcting code, the base correcting code and the maximized linear correcting code being associated with one and the same parity matrix H, the matrix being used to generate syndromes, the syndromes being used for decoding code words. The method comprises a step of identifying the syndromes unused for decoding the base linear correcting code, a step of identifying the errors that can affect the code words and make it possible to obtain the unused syndromes when a code word is multiplied by the matrix H and a step of selecting a unique error for each unused syndrome from among the identified errors, the error being called additional error.

Abstract: An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H·V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k>k1>2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method.

Abstract: A method for protecting digital memory against permanent and transient errors and a related device, the digital data being stored in at least one storage matrix of memory cells in a given number of rows and columns, comprises: an encoding step generating code words from data organized in binary words by application of asymmetric code introducing at least two different levels of protection, the first level of protection said to be high being associated with a first sub-group of bits of the code word and a second level of protection said to be low being associated with a second sub-group of the same word; swapping positions of the bits of the code word making the bits with a high level of protection correspond for their storage to the columns of the storage area comprising defective memory cells and the bits with a low level of protection to the remaining columns.

Abstract: An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H·V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k>k1>2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method.

Abstract: A router in which each of the input/output ports is associated with identifiers enabling each of the other input/output ports to locate it according to a code specific to each of them, comprising means for identifying in an incident packet a routing instruction indicating a forward identifier of the desired output port; and means for sending back the packet where the forward identifier is suppressed from the routing instruction and a return identifier is inserted therein.