Abstract: A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for transmitting and integrating an intellectual property (IP) block with another user's design. The IP developer can design the IP block to include both a secret portion and a public portion. The IP block developer can send or otherwise provide the IP block to another IP user without disclosing the functional description of the secret portion of the IP block. In some implementations, the IP developer provides the public portion to the IP user at the register-transfer-level (RTL) level, as a hardware description language (HDL)-implemented design, or as a synthesizable netlist. In some implementations, the IP developer provides the secret portion of the IP block to the user in the form of programming bits without providing an HDL, RTL, or netlist implementation of the secret portion.

Abstract: Techniques for live-writing and editing closed captions are disclosed. In one particular embodiment, the techniques may be realized as a method for generating captions for a live broadcast comprising the steps of receiving audio data, the audio data corresponding to words spoken as part of the live broadcast; analyzing the audio data with speech recognition software in order to generate unedited captions; and generating edited captions from the unedited captions, wherein the edited captions reflect edits made by a user. All of these steps may be performed during the live broadcast.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for transmitting and integrating an intellectual property (IP) block with another user's design. The IP developer can design the IP block to include both a secret portion and a public portion. The IP block developer can send or otherwise provide the IP block to another IP user without disclosing the functional description of the secret portion of the IP block. In some implementations, the IP developer provides the public portion to the IP user at the register-transfer-level (RTL) level, as a hardware description language (HDL)-implemented design, or as a synthesizable netlist. In some implementations, the IP developer provides the secret portion of the IP block to the user in the form of programming bits without providing an HDL, RTL, or netlist implementation of the secret portion.

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.

Abstract: A programmable chip design tool is provided to enumerate and specify the security and/or redundancy constraints of a programmable chip design. A design is implemented with a high-level security or redundancy scheme, and the programmable chip design tool applies the scheme while simultaneously optimizing for desired metrics (logic density, routability, timing, power, etc.). An underlying assignment scheme as well as user interface components used to enter this assignment scheme are provided.

Abstract: Method of treating autoimmune conditions are disclosed comprising administering to a mammalian subject IL-12 or an IL-12 antagonist. In certain preferred embodiments the autoimmune condition is one which is promoted by an increase in levels of IFN-? or TNF-?. Suitable conditions for treatment include multiple sclerosis, systemic lupus erythematosus, rheumatoid arthritis, autoimmune pulmonary inflammation, Guillain-Barre syndrome, autoimmune thyroiditis, insulin dependent diabetes melitis and autoimmune inflammatory eye disease.

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.

Abstract: Mechanisms are provided to prevent information leakage between components implemented on a programmable chip such as a Field Programmable Gate Array (FPGA). An automated routing algorithm is effective at enforcing security restrictions with minimal input form the user while providing efficient utilization of the device. Compatible sets of signals are identified and locked, and reservations of routing resources are generated. Remaining signals are rerouted until all signal constraints are met. Specified security constraints with one or more security levels and one or more secure regions may be applied through iterations of the automated routing mechanism.

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Abstract: Method of treating autoimmune conditions are disclosed comprising administering to a mammalian subject IL-12 or an IL-12 antagonist. In certain preferred embodiments the autoimmune condition is one which is promoted by an increase in levels of IFN-? or TNF-?. Suitable conditions for treatment include multiple sclerosis, systemic lupus erythematosus, rheumatoid arthritis, autoimmune pulmonary inflammation, Guillain-Barre syndrome, autoimmune thyroiditis, insulin dependent diabetes melitis and autoimmune inflammatory eye disease.