Abstract: A variable slope delta coding processor using adaptive prediction in which a digitized signal is transmitted with approximately half the channel bandwidth required by previous techniques without any substantial sacrifice of received signal quality. An estimate of a digital sample is subtracted from a digital sample of an input signal to produce an error signal. The sign bit of the error signal is transmitted as a single bit output signal. A predetermined number of immediately adjacent single bit output signals are utilized to calculate an adaptive step value using a compression technique. A set of reconstructed signal values is built up, one for each of the input signal, with each reconstructed signal value being calculated as the sum of the adaptive step size value and the estimate of the sample of the input signal. For each new sample of the input signal, an oldest reconstructed signal value is discarded and replaced by a newly calculated value.