Patents by Inventor Samuel J. Peters, II
Samuel J. Peters, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10476659Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digiType: GrantFiled: July 30, 2018Date of Patent: November 12, 2019Assignee: AVNERA CORPORATIONInventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
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Publication number: 20190140816Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digiType: ApplicationFiled: July 30, 2018Publication date: May 9, 2019Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
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Patent number: 10038548Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digiType: GrantFiled: October 31, 2017Date of Patent: July 31, 2018Assignee: AVNERA CORPORATIONInventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
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Publication number: 20180054297Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digiType: ApplicationFiled: October 31, 2017Publication date: February 22, 2018Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
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Patent number: 9832012Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.Type: GrantFiled: April 11, 2017Date of Patent: November 28, 2017Assignee: AVNERA CORPORATIONInventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
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Publication number: 20170222793Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.Type: ApplicationFiled: April 11, 2017Publication date: August 3, 2017Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
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Patent number: 9621336Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.Type: GrantFiled: August 28, 2014Date of Patent: April 11, 2017Assignee: AVNERA CORPORATIONInventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
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Publication number: 20140270028Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: Avnera CorporationInventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hanson, Alexander C. Stange
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Patent number: 7600144Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.Type: GrantFiled: August 22, 2006Date of Patent: October 6, 2009Inventors: Victor Hansen, Erik Landerholm, Samuel J. Peters, II
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Patent number: 7433303Abstract: In a network apparatus, control logic is provided to preemptively issue pause controls to a sender of network traffic of a link to preemptively regulate a rate the sender may send network traffic of the link. In one embodiment, the pause controls are sent periodically, with each including a pause duration. In one embodiment, at least a selected one of the pause duration and the periodicity of preemptive issuance is determined based at least in part on at least a selected one of a working capacity of storage medium allocated to service the link, a network traffic drain rate of the link, and a fill rate of the input line over which the network traffic of the link is received. In one embodiment, the networking apparatus is an optical networking module with the control logic disposed in a multi-protocol networking processor of the module.Type: GrantFiled: August 2, 2002Date of Patent: October 7, 2008Assignee: Null Networks LLCInventors: Alfred C. She, Samuel J. Peters, II, I. Claude Denton
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Patent number: 7100067Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.Type: GrantFiled: March 19, 2003Date of Patent: August 29, 2006Inventors: Victor Hansen, Erik Landerholm, Samuel J. Peters, II