Patents by Inventor Samuel J. Tower

Samuel J. Tower has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pulsed state retention power gating flip-flop
    Patent number: 8289060
    Abstract: A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: October 16, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Samuel J. Tower, Matthew S. Berzins, Charles A. Cornell
  • Flip-flop having logic state retention during a power down mode and method therefor
    Patent number: 7583121
    Abstract: A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: September 1, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Matthew S. Berzins, Charles A. Cornell, Samuel J. Tower
  • FLIP-FLOP HAVING LOGIC STATE RETENTION DURING A POWER DOWN MODE AND METHOD THEREFOR
    Publication number: 20090058485
    Abstract: A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 5, 2009
    Inventors: Matthew S. Berzins, Charles A. Cornell, Samuel J. Tower
  • PULSED STATE RETENTION POWER GATING FLIP-FLOP
    Publication number: 20080315932
    Abstract: A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Inventors: Samuel J. Tower, Matthew S. Berzins, Charles A. Cornell